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User Guide

Altera Transceiver PHY IP Core

Document last updated for Altera Complete Design Suite version:

Document publication date:

10.1

December 2010

Altera Transceiver PHY IP Core User Guide

Summary of content (120 pages)

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Altera Transceiver PHY IP Core User Guide Altera Transceiver PHY IP Core User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01080-1.11 Document last updated for Altera Complete Design Suite version: Document publication date: 10.
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Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other words and logos identified as trademarks and/or service marks are the property of Altera Corporation or their respective owners. Altera products are protected under numerous U.S.
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Contents Chapter 1. Introduction PCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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iv Contents Chapter 5. Interlaken PHY IP Core Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents v Avalon-ST TX and RX Data Interface to the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6 Avalon-MM PHY Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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vi Altera Transceiver PHY IP Core User Guide Contents December 2010 Altera Corporation
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1. Introduction The Altera® Transceiver PHY IP Core User Guide describes the following protocol-specific PHYs: ■ 10GBASE-R PHY IP Core ■ XAUI PHY IP Core ■ Interlaken PHY IP Core ■ PCI Express PHY (PIPE) IP Core ■ Custom PHY IP Core ■ Low Latency PHY IP Core The protocol-specific PHYs automatically configure settings for the physical coding sublayer (PCS) module, leaving a small number of parameters in the physical media attachment (PMA) module for you to configure.
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1–2 Chapter 1: Introduction Figure 1–1 illustrates the top level modules that comprise the PHY IP cores. Figure 1–1.
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Chapter 1: Introduction PCS 1–3 The following sections provide a brief introduction to each of the modules illustrated in Figure 1–1. PCS The PCS implements part of the physical layer specification for networking protocols. Depending upon the protocol that you choose, the PCS may include many different functions.
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1–4 Chapter 1: Introduction Reset Controller Figure 1–2.
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Chapter 1: Introduction Reset Controller 1–5 In non-bonded mode, separate CGBs are used for each channel and the skew between channels is not carefully controlled. Figure 1–3 illustrates mode for Stratix V devices. Figure 1–3.
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1–6 Chapter 1: Introduction Reset Controller The reset controller also includes a signal to power down the PLLs and transceiver channels: ■ 1 pll_powerdown—This signal powers down a single clock generation circuit. pll_powerdown is only asserted during a full reset sequence, which is only possible when the device enters user mode or when you assert and deassert the PHY management interface reset input.
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Chapter 1: Introduction Reset Controller 1–7 3. Finally, rx_ready is asserted and phy_mgmt_clk_reset goes low, ending the reset state. \ Figure 1–4. Reset Sequence phy_mgmt_clk phy_mgmt_clk_reset pll_islocked rx_oc_busy rx_islocked_toref powerdown_all tx_ready rx_ready Figure 1–5 shows the hardware modules and internal signals that implement reset in Stratix V devices. Figure 1–5.
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1–8 Chapter 1: Introduction Avalon-MM PHY Management Avalon-MM PHY Management You can use the Avalon-MM PHY Management module to read and write the control and status registers in the PCS and PMA. This module includes both Avalon-MM master and slave ports and acts as a bridge. It transfers commands received from an embedded controller on its slave port to its master port.
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2. Getting Started This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications.
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2–2 Chapter 2: Getting Started MegaWizard Plug-In Manager Flow ■ MegaWizard Plug-In Manager Flow Figure 2–2.
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Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 2–3 3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the “Parameter Settings” chapter in this document. 1 Some IP cores provide preset parameters for specific applications.
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2–4 Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 8. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments.
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3. 10GBASE-R PHY IP Core The Altera 10GBASE-R PHY IP core implements the functionality described in IEEE 802.3 Clause 49. It delivers serialized data to an optical module that drives multi-mode optical fiber at a line rate of 10.3125 Gbps. In a multi-channel implementation of 10GBASE-R, each channel of the 10GBASE-R PHY IP core operates independently. You can instantiate multiple channels to achieve higher bandwidths.
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3–2 Chapter 3: 10GBASE-R PHY IP Core To make most effective use of this soft PCS and hard PMA configuration, you can group up to four channels in a single quad and control their functionality using one Avalon-MM PHY management bridge, transceiver reconfiguration module, and low latency controller.
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Chapter 3: 10GBASE-R PHY IP Core Release Information 3–3 Release Information Table 3–1 provides information about this release of the 10GBASE-R PHY IP core. Table 3–1. 10GBASE-R Release Information Item Description Version 10.1 Release Date December 2010 Ordering Codes (Note 1) IP-10GBASERPCS (primary) IPR-10GBASERPCS (renewal) Product ID 00D7 Vendor ID 6AF7 Note to Figure 3–1: (1) No ordering codes or license files are required for Stratix V devices.
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3–4 Chapter 3: 10GBASE-R PHY IP Core Performance and Resource Utilization Performance and Resource Utilization Table 3–3 shows the typical expected device resource utilization for a single duplex channel using the current version of the Quartus II software targeting a Stratix IV GT device. The numbers of combinational ALUTs, logic registers, and memory bits are rounded to the nearest 100. Table 3–3.
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Chapter 3: 10GBASE-R PHY IP Core Interfaces 3–5 Interfaces Figure 3–3 illustrates the top-level signals of the 10Base-R PHY. 1 The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the Hardware Component Description File (_hw.tcl). f For more information about _hw.tcl files, refer to the Component Interface Tcl Reference chapter in the SOPC Builder User Guide. Figure 3–3.
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3–6 Chapter 3: 10GBASE-R PHY IP Core Interfaces SDR XGMII TX Interface Table 3–5 describes the signals in the SDR XGMII TX interface. These signals are driven from the MAC to the PCS. This is an Avalon-ST sink interface. Table 3–5. SDR XGMII TX Inputs (Note 1) Signal Name Direction Description Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control.
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Chapter 3: 10GBASE-R PHY IP Core Interfaces 3–7 Table 3–6.
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3–8 Chapter 3: 10GBASE-R PHY IP Core Interfaces Table 3–8.
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Chapter 3: 10GBASE-R PHY IP Core Interfaces 3–9 Register Descriptions Table 3–10 specifies the registers that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers. Table 3–10.
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3–10 Chapter 3: 10GBASE-R PHY IP Core Interfaces Table 3–10. 10GBASE-R Register Descriptions (Part 2 of 3) Word Addr Bit R/W Name Description PMA Channel Control and Status 0x061 [31:0] RW pma_serial_loopback Writing a 1 to channel puts channel in serial loopback mode. 0x063 [31:0] R pma_rx_signaldetect When asserted, the signal level circuit senses if the specified voltage level exists at the receiver input buffer. Bit corresponds to channel .
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Chapter 3: 10GBASE-R PHY IP Core Interfaces 3–11 Table 3–10. 10GBASE-R Register Descriptions (Part 3 of 3) Word Addr Bit [5:0] R/W R Name Description Records the bit error rate (BER). Not available for Stratix V devices. BER_COUNT From block: BER monitor 0x083 [7:0] R ERROR_BLOCK_COUNT Records the number of blocks that contain errors. Not available for Stratix V devices. From Block: Block synchronizer Status Interface Table 3–11 describes signals that provide status information. Table 3–11.
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3–12 Chapter 3: 10GBASE-R PHY IP Core Interfaces When connected to the hard PMA, the PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You must provide the PMA a input reference clock running at 644.53725MHz to generate the 257.8125 MHz clock. Figure 3–4 illustrates the clock generation and distribution for Stratix IV devices. Figure 3–4.
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Chapter 3: 10GBASE-R PHY IP Core Interfaces 3–13 Figure 3–5 illustrates the clock generation and distribution for Stratix V devices. Figure 3–5. Stratix V Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Stratix V GT TX 64 xgmii_tx_clk 10.3125 Gbps serial 40 TX PCS TX PMA 257.8125 MHz RX 64 xgmii_rx_clk TX PLL 10.3125 Gbps serial 40 RX PCS pll_ref_clk 644.53125 MHz RX PMA 257.8125 MHz 156.
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3–14 Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints Serial Interface Table 3–13 describes the input and outputs of the transceiver. Table 3–13.
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Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints 3–15 Example 3–1 provides the Synopsys Design Constraints File (.sdc) timing constraints for the 10GBASE-R IP core. To pass timing analysis, you must decouple the clocks in different time domains. Be sure to verify the each clock domain is correctly buffered in the top level of your design. You can find the .sdc file in your top-level working directory. This is the same directory that includes your top-level .v or .vhd file. Example 3–1.
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3–16 Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints Synopsys Design Constraints for Clocks (continued) ##************************************************************** # Set False Path #************************************************************** set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|rx_pma_rstn} -to [get_clocks {{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout} {*siv_alt_pma|pma_ch*.
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4. XAUI PHY IP Core The Altera XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals. XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function implemented in an Altera FPGA and the Ethernet standard PHY component on a PCB to one meter. Figure 4–1 illustrates the top-level blocks of the XAUI PHY for Stratix IV GX or Stratix V devices. Figure 4–1.
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4–2 Chapter 4: XAUI PHY IP Core Device Family Support Table 4–1. XAUI Release Information (Part 2 of 2) Item Description Vendor ID 6AF7 Note to Table 4–1: (1) No ordering codes or license files are required for the hard PCS and hard PMA PHY in Arria II GX, Cyclone IV GX, or Stratix IV GX or GT devices. Device Family Support IP cores provide either final or preliminary support for target Altera device families.
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Chapter 4: XAUI PHY IP Core Parameter Settings 4–3 Parameter Settings To configure the XAUI IP core in the parameter editor, click Installed Plug-Ins > Interfaces >Ethernet> XAUI PHY v10.1. This section describes the XAUI PHY IP core parameters, which you can set using the parameter editor. Table 4–4 lists the settings available on General Options tab. Table 4–4. General Options Name Value Description Arria II GX Cyclone IV GX Stratix IV Stratix V The target device family.
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4–4 Chapter 4: XAUI PHY IP Core Configurations For a description of the PMA analog options, refer to “PMA Analog Options” on page 8–4. Configurations Figure 4–2 illustrates one configuration of the XAUI IP core. As this figure illustrates, if your variant includes a single instantiation of the XAUI IP core, the transceiver reconfiguration control logic is included in the XAUI PHY IP core. Figure 4–2.
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Chapter 4: XAUI PHY IP Core Interfaces 4–5 Interfaces Figure 4–3 illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementation which is available for Stratix IV GX and Stratix V devices. Figure 4–4 illustrates the top-level signals of the XAUI PHY IP core for the hard IP implementation which is available for Stratix IV GX devices. With the exception of the optional signals available for debugging, the pinout of the two implementations is nearly identical.
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4–6 Chapter 4: XAUI PHY IP Core Interfaces Figure 4–4 illustrates the top-level signals of the XAUI PHY IP core for the hard IP implementation which is available for Arria II GX, Cyclone IV GX, and Stratix IV GX devices. Figure 4–4.
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Chapter 4: XAUI PHY IP Core Interfaces 4–7 This interface runs at 156.25 MHz in accordance with XGMII specification; however, data is only driven on the rising edge of clock. To meet the bandwidth requirements, the datapath is eight bytes wide with eight control bits, instead of the standard four bytes of data and four bits of control. The XAUI IP core treats the datapath as two, 32-bit data buses and includes logic to interleave them, starting with the low-order bytes. Figure 4–5 illustrates the mapping.
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4–8 Chapter 4: XAUI PHY IP Core Interfaces Avalon-MM Interface The Avalon-MM PHY management block includes master and slave interfaces. This component acts as a bridge. It transfers commands received on its Avalon-MM slave interface to its Avalon-MM port. This interface provides access to the PCS and PMA registers, the Transceiver Reconfiguration, and the Low Latency PHY Controller IP cores. Table 4–8 describes the signals that comprise the Avalon-MM PHY Management interface. Table 4–8.
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Chapter 4: XAUI PHY IP Core Interfaces 4–9 Table 4–9. XAUI PHY IP Core Registers (Part 2 of 4) Word Addr 0x042 Bits R/W Register Name W reset_control (write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask. R reset_status(read) Reading bit 0 returns the status of the reset controller TX ready bit.
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4–10 Chapter 4: XAUI PHY IP Core Interfaces Table 4–9. XAUI PHY IP Core Registers (Part 3 of 4) Word Addr Bits R/W Register Name Description XAUI PCS [31:2] 0x081 — [1] tx_digital reset RW [0] 0x082 Reserved rx_digital reset [31:4] — Reserved [3:0] RW invpolarity[3:0] — Resets the TX PCS clock domain. To block: RX PCS. Resets the RX PCS clock domain. To block: TX PCS. — Inverts the polarity of corresponding bit on the RX interface. Bit 0 maps to lane 0 and so on. To block: Word aligner.
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Chapter 4: XAUI PHY IP Core Interfaces 4–11 Table 4–9. XAUI PHY IP Core Registers (Part 4 of 4) Word Addr Bits [31:8] R/W — Register Name Description Reserved — Indicates a RX phase compensation FIFO overflow or phase_comp_fifo_error[3: underrun condition on the corresponding lane. Reading the value of the phase_comp_fifo_error register clears the 0] bits. [7:4] 0x086 From block: RX phase compensation FIFO. R, sticky rlv[3:0] [3:0] Indicates a run length violation.
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4–12 Chapter 4: XAUI PHY IP Core Interfaces Transceiver Serial Data Interface Table 4–10 describes the signals in the XAUI transceiver serial data interface. There are four lanes of serial data for both the TX and RX interfaces. This interface runs at 3.125 GHz. There is no separate clock signal because it is encoded in the data. Table 4–10. Serial Data Interface Signal Name Direction Description xaui_rx_serial_data[3:0] Input Serial input data. xaui_tx_serial_data[3:0] Output Serial output data.
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Chapter 4: XAUI PHY IP Core Interfaces 4–13 Clocks, Reset, and Powerdown Figure 4–6 illustrates the clock inputs and outputs for the XAUI IP cores with hard PCS and PMA blocks. Figure 4–6. Clock Inputs and Outputs, Hard PCS phy_mgmt_clk XAUI Hard IP Core pll_ref_clk pll_inclk Hard PCS xgmii_tx_clk rx_cruclk PMA 4 tx_coreclk xgmii_rx_clk 4 coreclkout 4 x 3.125 Gbps serial Figure 4–7 illustrates the clock inputs and outputs for the XAUI IP cores with soft PCS and PMA blocks. Figure 4–7.
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4–14 Chapter 4: XAUI PHY IP Core Interfaces PMA Channel Controller Table 4–13 describes the signals in this interface. Table 4–13. Low Latency PHY Controller Signal Name Direction Description cal_blk_powerdown Input Powers down the calibration block. A high-to-low transition on this signal restarts calibration. Only available in Arria II GX and Stratix IV GX, and Stratix IV GT devices. gxb_powerdown Input When asserted, powers down the entire transceiver block.
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Chapter 4: XAUI PHY IP Core Interfaces 4–15 PMA Control and Status Interface Signals–Hard IP Implementation (Optional) Table 4–15 lists the PMA control and status signals. You can access the state of these signals using the Avalon-MM PHY Management interface to read the control and status registers which are detailed in Table 4–9 on page 4–8. However, in some cases, you may need to know the instantaneous value of a signal to ensure correct functioning of the XAUI PHY.
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4–16 Chapter 4: XAUI PHY IP Core TimeQuest Timing Constraints Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part 2 of 2) Signal Name Direction Description Output Indicates that the word alignment pattern programmed has been detected in the current word boundary. The rx_patterndetect signal is 2 bits wide per channel for a total of 8 bits per XAUI link. Output Status flag that is asserted when the rate match block deletes a ||R|| column.
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Chapter 4: XAUI PHY IP Core TimeQuest Timing Constraints 4–17 Synopsys Design Constraints for Clocks (continued) #****** Use this section for Stratix V Soft XAUI ****** #create_generated_clock -name {xgmii_rx_clk_0} -source [get_pins -compatibility_mode {*alt_pma_0|alt_pma_sv_inst|sv_xcvr_generic_inst|channel_tx[0].duplex_pcs|ch[0].
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4–18 Altera Transceiver PHY IP Core User Guide Chapter 4: XAUI PHY IP Core TimeQuest Timing Constraints December 2010 Altera Corporation
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5. Interlaken PHY IP Core Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. The Altera Interlaken PHY IP core implements Interlaken Protocol Specification, Rev 1.2. It supports multiple instances, each with 1–24 lanes running at up to 10.3125 Gbps on Stratix V devices. The key advantage of Interlaken is its low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking.
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5–2 Chapter 5: Interlaken PHY IP Core Device Family Support f For more detailed information about the Interlaken transceiver channel datapath, clocking, and channel placement, refer to the “Interlaken” section in the Transceiver Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook. Device Family Support IP cores provide either final or preliminary support for target Altera device families.
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Chapter 5: Interlaken PHY IP Core Interface 5–3 Table 5–3. Parameters Parameter Datapath mode Value Duplex, RX, TX Description Specifies the mode of operation as Duplex, RX, or TX mode. Specifies the link bandwidth. The following table specifies the frequency of the reference clock you must provide to achieve these lane rates and the corresponding PCS frequency. Lane rate 3125 Mbps 5000 Mbps 6250 Mbps 6375 Mbps 10312.
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5–4 Chapter 5: Interlaken PHY IP Core Interface f For more information about _hw.tcl, files refer to the Component Interface Tcl Reference chapter in Volume 4 of the Quartus II Handbook. Figure 5–2.
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Chapter 5: Interlaken PHY IP Core Interface 5–5 Table 5–4. Avalon-ST TX Signals Signal Name Direction Description tx_clkout Output Output clock from the PCS. tx_user_clkout Output Master channel tx_clkout is available when you do not create the optional tx_coreclkin. Avalon-ST RX Interface Table 5–5 describes the signals in the Avalon-ST RX interface. Table 5–5.
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5–6 Chapter 5: Interlaken PHY IP Core Interface Avalon Memory-Mapped (Avalon-MM) Management Interface The Avalon-MM PHY management block includes master and slave interfaces. This component acts as a bridge. It transfers commands received on its Avalon-MM slave interface to its Avalon-MM port. This interface manages PCS and PMA modules, resets, error handling, and serial loopback controls. Table 5–6 describes the signals that comprise the Avalon-MM PCS management interface. Table 5–6.
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Chapter 5: Interlaken PHY IP Core Interface 5–7 Table 5–7. Interlaken Registers (Part 2 of 3) Word Addr Bits [31:4,0] 0x044 [1] [2] [3] R/W RW RW RW RW Register Name Description reset_fine_control You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Figure 1–1 on page 1–2, performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved.
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5–8 Chapter 5: Interlaken PHY IP Core Interface Table 5–7. Interlaken Registers (Part 3 of 3) Word Addr Bits R/W Register Name Description Stratix V Device Registers [23:0] — Reserved [24] R rx_word_lock [25] R — rx_sync_lock Asserted when the first alignment pattern is found. The RX FIFO generates this synchronous signal. Asserted by the frame synchronizer to indicate that 4 sync words have been identified so that the RX metaframe is synchronized. From block: Frame synchronizer.
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Chapter 5: Interlaken PHY IP Core Simulation Testbench 5–9 Optional Clocks for Deskew Table 5–10 describes the optional clocks that you can create to reduce clock skew. Table 5–10. Serial Interface Signal Name tx_coreclkin rx_coreclkin Direction Description Input When enabled tx_coreclkin is available as input port which drives the write side of TX FIFO. Altera recommends using this clock to reduce clock skew. When disabled, tx_cllkout drives the write side the TX FIFO.
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5–10 Chapter 5: Interlaken PHY IP Core Simulation Testbench Table 5–11. Generated Files File Name Description alt_interlaken_pcs_top.v The top-level static Verilog HDL file for the Interlaken PHY IP core. It includes parameterized port widths. altera_wait_generate.v Generates waitrequest for alt_interlaken_pcs. alt_interlaken_pcs_sv.v The transceiver core and memory-mapped logic for specified number of lanes for PMA and PLLs. amm_slave.v The Avalon-MM slave logic. alt_reset_ctrl_tgx_cdrauto.
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Chapter 5: Interlaken PHY IP Core Simulation Testbench 5–11 Example 5–1.
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5–12 Altera Transceiver PHY IP Core User Guide Chapter 5: Interlaken PHY IP Core Simulation Testbench December 2010 Altera Corporation
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6. PCI Express PHY (PIPE) IP Core The Altera PCI Express PHY (PIPE) IP core implements physical coding sublayer (PCS) and physical media attachment (PMA) modules as defined by the Intel PHY Interface for PCI Express (PIPE) Architecture specification. The PCI Express PHY (PIPE) connects to a PCI Express PHYMAC to create a complete PCI Express design. Altera supports the Gen1 and Gen2 specifications and ×1, ×2, ×4, or ×8 operation for a total aggregate bandwidth of 2–32 Gbps.
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6–2 Chapter 6: PCI Express PHY (PIPE) IP Core Resource Utilization Resource Utilization Table 6–2 shows the typical expected device resource utilization for different configurations using the current version of the Quartus® II software targeting a Stratix V GX device. Table 6–2.
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Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces 6–3 Interfaces Figure 6–2 illustrates the top-level pinout of the PCI Express PHY (PIPE) IP core. Figure 6–2.
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6–4 Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Avalon-ST TX Input Data from PCI Express PHYMAC Table 6–4 describes the signals in the Avalon-ST input interface. These signals are driven from the PCI Express PHYMAC to the PCS. This is an Avalon sink interface. f For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications. Table 6–4.
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Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces 6–5 Figure 6–3 illustrates the internal modules of the PCI Express PHY (PIPE) IP core. Figure 6–3.
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6–6 Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces PHY Management Signals Table 6–6 describes the signals that comprise the Avalon-MM PHY Management interface. Table 6–6. Avalon-MM PHY Management Interface Signal Name Direction Description phy_mgmt_clk Input Avalon-MM clock input. phy_mgmt_clk_reset Input Global reset signal that resets the entire PHY (PIPE). A positive edge on this signal triggers the reset controller.
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Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces 6–7 Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 2 of 4) Word Addr Bits [31:4,0] 0x044 [1] [2] [3] R/W RW RW RW RW Register Name Description reset_fine_control You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Figure 1–1 on page 1–2, performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved.
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6–8 Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 3 of 4) Word Addr 0x081 Bits R/W [31:6] R [5:1] R Register Name Description Reserved rx_bitslipboundary selectout — Records the number of bits slipped by the RX Word Aligner to achieve word alignment. Used for very latency sensitive protocols. From block: Word aligner.
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Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces 6–9 Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 4 of 4) Word Addr Bits R/W Register Name [31:20] R Reserved [19:16] R rx_rlv [15:12] R rx_patterndetect Description — When set, indicates a run length violation. From block: Word aligner. When set, indicates that RX word aligner has achieved synchronization. From block: Word aligner.
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6–10 Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Table 6–8. PIPE Interface (Part 2 of 2) Signal Name Direction Sink pipe_txcompliance Description When asserted for one cycle, sets the 8B/10B encoder output running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11 of the Intel PHY Interface for PCI Express (PIPE) Architecture for more information. Sink pipe_txmargin Transmit VOD margin selection.
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Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces 6–11 Figure 6–4 illustrates the pipe_pclk switching from Gen1 to Gen2 and back to Gen1. Figure 6–4. Rate Switch from Gen1 to Gen2 250 MHz (Gen1) 500 MHz (Gen2) 250 MHz (Gen1) pipe_pclk pipe_rate T1 T1 pipe_phystatus[-1:0] Note to Figure 6–4: (1) Time T1 is pending characterization. (2) is the number of lanes. Transceiver Serial Interface Table 6–9 describes the differential serial TX and RX connections to FPGA pins. Table 6–9.
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6–12 Chapter 6: PCI Express PHY (PIPE) IP Core Simulation Simulation When you generate your PCIe PIPE IP core, the Quartus II software generates the HDL files that define your parameterized IP core. In addition, the Quartus II software generates an example Tcl test script to compile and simulate your design. Figure 6–5 illustrates the directory structure for the generated files. Figure 6–5. Directory Structure for Generated Files .v or .
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Chapter 6: PCI Express PHY (PIPE) IP Core Simulation 6–13 Example 6–1 shows the part of the Tcl script that you must edit. Example 6–1.
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6–14 Altera Transceiver PHY IP Core User Guide Chapter 6: PCI Express PHY (PIPE) IP Core Simulation December 2010 Altera Corporation
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7. Custom PHY IP Core The Altera Custom PHY IP core is a generic PHY that you can customize for use in Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.600–8.5 Gbps. You can parameterize the physical coding sublayer (PCS) to include the functions that your application requires.
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7–2 Chapter 7: Custom PHY IP Core Performance and Resource Utilization ■ Preliminary support—Verified with preliminary timing models for this device. Table 7–1 shows the level of support offered by the Custom PHY IP core for Altera device families Table 7–1.
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Chapter 7: Custom PHY IP Core Parameter Settings 7–3 Table 7–2.
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7–4 Chapter 7: Custom PHY IP Core Parameter Settings Figure 7–3 shows the top-level interfaces when you disable Avalon data interfaces. Figure 7–3. Custom PHY with Avalon Interfaces Enabled 8B/10B Encoder and Decoder The 8B/10B encoder generates 10-bit code groups (control or data word) with proper disparity from the 8-bit data and 1-bit control identifier. The 8B/10B decoder receives 10-bit data from the rate matcher and decodes it into an 8-bit data + 1-bit control identifier.
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Chapter 7: Custom PHY IP Core Parameter Settings 7–5 Word Alignment The word aligner restores word boundaries of received data based on a predefined alignment pattern. This pattern can be 7, 8, 10, 16, 20, or 32 bits long. The word alignment module searches for a programmed pattern to identify the correct boundary for the incoming stream. Table 7–4 lists the settings available on the Word Aligner tab. Table 7–4.
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7–6 Chapter 7: Custom PHY IP Core Parameter Settings Table 7–5 provides more information about the word alignment function. Table 7–5. Word Aligner Options Configuration PMA-PCS Interface Width (bits) 8 Word Alignment Mode Word Alignment Pattern Length (bits) Manual alignment 16 User-controlled signal starts alignment process. Alignment occurs once unless signal is re-asserted. Bit-slip 16 User-controlled signal shifts data 1 bit at a time.
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Chapter 7: Custom PHY IP Core Parameter Settings 7–7 If you enable the rate match FIFO, the parameter editor provides options to enter the rate match insertion and deletion patterns. The lower 10 bits are the control pattern, and the upper 10 bits are the skip pattern. Table 7–6 lists the settings available on the Rate Match tab. Table 7–6.
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7–8 Chapter 7: Custom PHY IP Core Interfaces Table 7–8 lists the Datapath options. Table 7–8. Datapath Options Name Value Deserializer block width Deserializer actual width Description Specifies the mode of operation for the deserializer which clocks in serial input data from the RX buffer using the high-speed recovered clock and deserializes it using the low-speed parallel recovered clock. Forwards deserialized data to the RX PCS channel.
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Chapter 7: Custom PHY IP Core Interfaces 1 7–9 The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl. f For more information about _hw.tcl files, refer to Component Interface Tcl Reference chapter in the SOPC Builder User Guide. The following sections describe the signals in each interface.
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7–10 Chapter 7: Custom PHY IP Core Interfaces Table 7–10. Avalon-ST RX Interface (Part 2 of 2) Signal Name Direction Source rx_runningdisp Input rx_enabyteord Description This status signal indicates the disparity of the incoming data. This signal is created if you turn On the Enable byte ordering block control option on the Byte Order tab. A byte ordering operation occurs whenever rx_enabyteord is asserted. To perform multiple byte ordering operations, deassert and reassert rx_enabyteord.
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Chapter 7: Custom PHY IP Core Interfaces 7–11 PHY Management Signals Table 7–11 describes the signals in the PHY Management interface. Table 7–11. Avalon-MM PHY Management Interface Signal Name Direction Description Avalon-MM clock input. The frequency range for the phy_mgmt_clk varies for different devices, as follows: Input phy_mgmt_clk ■ Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices: 37.
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7–12 Chapter 7: Custom PHY IP Core Interfaces Table 7–12. Low Latency PHY IP Core Registers (Part 2 of 3) Word Addr Bits [31:4,0] 0x044 [1] [2] [3] R/W RW RW RW RW Register Name Description reset_fine_control You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Figure 1–1 on page 1–2, performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved.
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Chapter 7: Custom PHY IP Core Interfaces 7–13 Table 7–12. Low Latency PHY IP Core Registers (Part 3 of 3) Word Addr Bits R/W [31:1] R [0] RW tx_phase_comp_fifo_error [31:6] RW pcs8g_tx_control Reserved. [0] RW tx_invpolarity When set, the TX interface inverts the polarity of the TX data. 0x082 0x083 Register Name Description Reserved. pcs8g_tx_status When set, indicates an TX phase compensation FIFO error. From block: TX phase Compensation FIFO To block: 8B/10B encoder.
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7–14 Chapter 7: Custom PHY IP Core Interfaces Transceiver Serial Data Interface Table 7–14 describes the differential serial data interface and the status signals for the RX interface. Table 7–14. Serial Interface and Status Signals Signal Name (Note 1) Direction rx_serial_data[-1:0] Input tx_serial_data[-1:0] Output Signal Name Receiver differential serial input data. Transmitter differential serial output data. Note to Table 7–14: (1) is the number of lanes.
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Chapter 7: Custom PHY IP Core Interfaces 7–15 Table 7–15. Serial Interface and Status Signals (Part 2 of 2) (Note 1) Signal Name rx_bitslipboundaryselectout Direction Output [-1:0] Signal Name This signal is used for bit slip word alignment mode. It reports the number of bits that the RX block slipped to achieve a deterministic latency. Note to Table 7–14: (1) is the number of lanes. is the deserialization factor. ~~is the symbol size in bits.~~
~~is the number of PLLs.~~
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~~7–16 Altera Transceiver PHY IP Core User Guide Chapter 7: Custom PHY IP Core Interfaces December 2010 Altera Corporation~~
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8. Low Latency PHY IP Core The Altera Low Latency IP core receives and transmits differential serial data, recovering the RX clock from the RX input stream. The PMA connects to a simplified PCS that whose single function doubles the width of the TX and RX datapaths. An Avalon-ST interface is used for TX and RX data for the MAC interface. An Avalon-MM interface provides access to control and status information. Figure 8–1 illustrates the top-level modules of the Low Latency PHY IP core. Figure 8–1.
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8–2 Chapter 8: Low Latency PHY IP Core Device Family Support Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: ■ Final support—Verified with final timing models for this device. ■ Preliminary support—Verified with preliminary timing models for this device. Table 8–1 shows the level of support offered by the PMA IP core for Altera device families. Table 8–1.
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Chapter 8: Low Latency PHY IP Core Parameter Settings 8–3 Table 8–2. General Options Name Value Enable lane bonding Avalon data interfaces Description On/Off When enabled, the PMA uses bonded clocks. On/Off When you turn this option on, there is a separate Avalon-ST bus for each lane which includes the control and status signals for that lane. Layout and transmission of data is big endian.
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8–4 Chapter 8: Low Latency PHY IP Core Parameter Settings Table 8–3. Additional Options (Part 2 of 2) Name Value Description Parameters for Stratix IV and Derivatives PLL type CMU, ATX Allows you to choose a clock multiplier unit (CMU) or auxiliary transmit (ATX) PLL. The CMU PLL is designed to achieve low TX channel-to-channel skew. The ATX PLL is designed to improve jitter performance. This option is only available for Stratix IV GX devices.
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Chapter 8: Low Latency PHY IP Core Interfaces 8–5 Table 8–4. PMA Analog Options (Part 2 of 2) Name Value RX termination resistance Description OCT_85_OHMS OCT_100_OHMS Indicates the value of the termination resistor for the receiver. OCT_120_OHMS OCT_150_OHMS Sets the equalization DC gain using one of the following settings: Receiver DC gain 0–4 Receiver static equalizer setting: ■ 0–0 dB ■ 1–3 dB ■ 2–6 dB ■ 3–9 dB ■ 4–12 dB This option sets the equalizer control settings.
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~~8–6 Chapter 8: Low Latency PHY IP Core Interfaces Figure 8–3 shows the interface connectivity of the PMA IP core. Figure 8–3.~~
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Chapter 8: Low Latency PHY IP Core Interfaces 8–7 Avalon-MM PHY Management Interface You can use the Avalon-MM PHY Management interface to read and write registers that control the TX and RX channels, the PMA powerdown and PLL registers, and loopback modes. Table 8–6 describes the signals in this interface. Table 8–6.
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8–8 Chapter 8: Low Latency PHY IP Core Interfaces Serial Data Interface Table 8–8 describes the signals that comprise the serial data interface. Table 8–8. Serial Data Interface Signal Name Direction Description rx_serial_data[:0] Sink Differential high speed input serial data. tx_serial_data [:0] Source Differential high speed output serial data. Note to Table 8–8: (1) is the number of modules connecting to the Transceiver Reconfiguration IP core.
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9. Transceiver Reconfiguration Controller You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure the TX and RX analog settings in Stratix IV GX devices. This modules is included in the Transceiver Toolkit, the XAUI PHY IP core, and the 10GBASE-R PHY IP core. Figure 9–1 shows the top-level modules of the Transceiver Reconfiguration Controller. f In Stratix IV devices, the PCI Express IP core uses a different reconfiguration IP core.
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9–2 Chapter 9: Transceiver Reconfiguration Controller Register Descriptions 1 During power-up, the Stratix IV GX devices perform offset cancellation for the RX channels to correct for process variations. You cannot reconfigure the PMA analog settings before this process completes. f Refer to Figure 1–4 on page 1–7 which illustrates the critical signals for the reset of a duplex channel. Register Descriptions Table 9–1 describes the analog Transceiver Reconfiguration control and status registers.
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Chapter 9: Transceiver Reconfiguration Controller Steps to Achieve PMA Controls Reconfiguration 9–3 Table 9–1. Dynamic Reconfiguration Control and Status Registers (Part 2 of 2) Offset 0x10C Bits R/W [15:0] RW reconfig_data [31:16] — Reserved 0x110 Register Name eye_monitor Description Reconfiguration data.
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~~9–4 Altera Transceiver PHY IP Core User Guide Chapter 9: Transceiver Reconfiguration Controller Steps to Achieve PMA Controls Reconfiguration December 2010 Altera Corporation~~
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10. Migrating from Stratix IV to Stratix V Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The current release of the Quartus II software includes protocol-specific PHY IP cores that simplify the parameterization process. The design of these protocol-specific transceiver PHYs is modular and uses standard interfaces. An Avalon-MM interface provides access to control and status registers that record the status of the PCS and PMA modules.
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10–2 Chapter 10: Migrating from Stratix IV to Stratix V XAUI PHY Table 10–1. Comparison ALTGX Megafunction and XAUI PHY Parameters (Part 2 of 2) ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name Comments Acceptable PPM threshold between receiver CDR VCO and receiver input reference clock (±1000) Analog power (Auto) Loopback option (No loopback) Enable static equalizer control (Off) DC gain (0) Receiver common mode voltage (0.
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~~Chapter 10: Migrating from Stratix IV to Stratix V XAUI PHY 10–3 Table 10–2.~~
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~~10–4 Chapter 10: Migrating from Stratix IV to Stratix V PCI Express PHY (PIPE) Table 10–2.~~
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~~Chapter 10: Migrating from Stratix IV to Stratix V PCI Express PHY (PIPE) 10–5 Table 10–3.~~
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~~10–6 Chapter 10: Migrating from Stratix IV to Stratix V PCI Express PHY (PIPE) Table 10–4.~~
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~~Chapter 10: Migrating from Stratix IV to Stratix V PCI Express PHY (PIPE) 10–7 Table 10–4.~~
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10–8 Chapter 10: Migrating from Stratix IV to Stratix V Custom PHY Custom PHY This section lists the differences between the parameters and signals for the Custom PHY IP core nd the ALTGX megafunction when configured in the Basic functional mode. Parameter Differences Table 10–5 lists the Custom PHY parameters and the corresponding ALTGX megafunction parameters. Table 10–5.
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Chapter 10: Migrating from Stratix IV to Stratix V Custom PHY 10–9 Port Differences Table 10–4 lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices. Table 10–6.
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~~10–10 Altera Transceiver PHY IP Core User Guide Chapter 10: Migrating from Stratix IV to Stratix V Custom PHY December 2010 Altera Corporation~~
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Additional Information This chapter provides additional information about the document and Altera. Revision History The table below displays the revision history for the chapters in this user guide. Date December 2010 Version 1.11 Changes Made SPR ■ Corrected frequency range for the phy_mgmt_clk for the Custom PHY IP core in Table 7–11 on page 7–11. ■ Added optional reconfig_fromgxb[67:0] to Figure 4–3 on page 4–5.
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Info–2 Additional Information Revision History Date Version Changes Made SPR Interlaken PHY Transceiver December 2010 1.1 ■ Added simulation support in ModelSim SE, Synopsys VCS MX, Cadence NCSim ■ Changed number of lanes supported from 4–24 to 1–24. ■ Changed reference clock to be 1/20th rather than 1/10th the lane rate. ■ Renamed management interface, adding phy_ prefix ■ Changed phy_mgmt_address from 16 to 9 bits. ■ Changed many signal names, refer to Figure 5–2 on page 5–4.
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Additional Information How to Contact Altera Date Info–3 Version November 2010 1.1 July 2010 1.0 Changes Made SPR ■ Corrected address offsets in Table 9–1 on page 9–2. These are byte offsets and should be: 0x00, 0x04, 0x08, 0x0C, 0x10, not 0x00, 0x01, 0x02, 0x03, 0x04. ■ Corrected base address for transceiver reconfiguration control and status registers in Table 9–1 on page 9–2. It should be 0x420, not 0x400. ■ Corrected byte offsets in Table 7–12 on page 7–11 and Table 6–7 on page 6–6.
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Info–4 Additional Information Typographic Conventions Visual Cue Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. The suffix n denotes an active-low signal. For example, resetn. Courier type Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.