User guide

Chapter 8: Low Latency PHY IP Core 8–7
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Avalon-MM PHY Management Interface
You can use the Avalon-MM PHY Management interface to read and write registers
that control the TX and RX channels, the PMA powerdown and PLL registers, and
loopback modes. Table 8–6 describes the signals in this interface.
Register Descriptions
Table 8–7 describes the registers that you can access over the PHY Management
Interface using word addresses and a 32-bit embedded processor.
Table 8–6. Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input
This clock signal that controls the Avalon-MM PHY management,
calibration, and reconfiguration interfaces. For Stratix IV devices,
the maximum frequency is 50 MHz. For Stratix V devices, the
maximum frequency is 150 MHz.
phy_mgmt_reset Input Global reset signal. A positive edge on this signal triggers a reset.
phy_mgmtaddress[8:0] Input 9-bit Avalon-MM address.
phy_mgmtwritedata[31:0] Input Input data.
phy_mgmtreaddata[31:0] Output Output data.
phy_mgmtwrite Input Write signal.
phy_mgmtread Input Read signal.
Table 8–7. PMA Channel Control and Status
Byte
Offset
Bits R/W Register Name Description
0x063 [31:0] R
pma_rx_signaldetect
When channel <n> =1, indicates that receive circuit for
channel <n> senses the specified voltage exists at the
RX input buffer. This option is only operational for the
PCI Express PHY IP core.
0x064 [31:0] RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
0x066 [31:0] R
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode. Bit <n> corresponds
to channel <n>.
0x067 [31:0] R
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR PLL is
locked to the reference clock. Bit <n> corresponds to
channel <n>.