User guide

8–8 Chapter 8: Low Latency PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Serial Data Interface
Table 8–8 describes the signals that comprise the serial data interface.
Optional Status Interface
Table 8–9 describes the signals that comprise the optional status interface.
Table 8–8. Serial Data Interface
Signal Name Direction Description
rx_serial_data[<n-1>:0] Sink Differential high speed input serial data.
tx_serial_data [<n-1>:0] Source Differential high speed output serial data.
Note to Table 8–8:
(1) <n> is the number of modules connecting to the Transceiver Reconfiguration IP core.
Table 8–9. Optional Status Interface
Signal Name Direction Description
rx_clkout[<n-1>:0] Output Low speed clock recovered from the serial data.
rx_is_lockedtodata[<n-1>:0] Output
When asserted, indicates that the RX CDR is locked to
incoming data. This signal is optional. If latency is not critical,
you can read the value of this signal from the
Rx_is_lockedtodata register.
rx_is_lockedtoref[<n-1>:0] Output
When asserted, indicates that the RX CDR is locked to the input
reference clock. This signal is optional. When the RX CDR is
locked to data, you can ignore transitions on this signal. If
latency is not critical, you can read the value of this signal from
the Rx_is_lockedtoref register.
pll_locked[<n-1>:0] Output
When asserted, indicates that the TX PLL is locked to the input
reference clock. This signal is asynchronous.
tx_coreclkin[<n-1>:0] Input
This is an optional clock to drive the write side of the TX PCS
FIFO.
rx_coreclkin[<n-1>:0] Input
This is an optional clock to drive the read side of the RX PCS
FIFO.
tx_bitslip Output
When set, the data sent to the PMA is slipped. The maximum
number of bits that can be slipped is equal to the value selected
in the serialization factor field - 1 or <d> -1.
Note to Table 8–9:
(1) <n> is the number of modules connecting to the Transceiver Reconfiguration IP core.