User guide

9–2 Chapter 9: Transceiver Reconfiguration Controller
Register Descriptions
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
1 During power-up, the Stratix IV GX devices perform offset cancellation for the RX
channels to correct for process variations. You cannot reconfigure the PMA analog
settings before this process completes.
f Refer to Figure 1–4 on page 1–7 which illustrates the critical signals for the reset of a
duplex channel.
Register Descriptions
Table 9–1 describes the analog Transceiver Reconfiguration control and status
registers.
Table 9–1. Dynamic Reconfiguration Control and Status Registers (Part 1 of 2)
Offset Bits R/W Register Name Description
0x108
[31:10] — Reserved —
[9:0] RW
logical_channel_address
The logical channel address. Must be specified when
performing dynamic updates.
0x109
[31:10] — Reserved —
[9:0] R
physical_channel_address The physical channel address.
0x10A
[31:10] — Reserved —
[9] RW
status
Error
. When asserted, indicates an error. This bit is
asserted if any of the following conditions occur:
■ The channel address is invalid.
■ The pre-emphasis value is invalid.
[8] RW
Busy . When asserted, indicates that the a reconfiguration
operation is in progress.
[7:2] — Reserved.
[1] RW
Read . Writing a 1 to this bit specifies a read operation.
[0] RW
Write . Writing a 1 to this bit specifies a write operation.
0x10B
[31:5] — Reserved —
[4:0] RW
tx_rx_word_offset
Specifies the offset of the PMA analog setting to be
reconfigured. The following analog settings are available:
■ 0–V
OD
■ 1–Pre-emphasis pre-tap
■ 2–Pre-emphasis first post-tap
■ 3-Pre-emphasis second post-tap
■ 4-15–reserved
■ 16–RX equalization DC gain
■ 17–RX equalization control
■ 13-18–reserved