User guide

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
10. Migrating from Stratix IV to Stratix V
Previously, Altera provided the ALTGX megafunction as a general purpose
transceiver PHY solution. The current release of the Quartus II software includes
protocol-specific PHY IP cores that simplify the parameterization process.
The design of these protocol-specific transceiver PHYs is modular and uses standard
interfaces. An Avalon-MM interface provides access to control and status registers
that record the status of the PCS and PMA modules. Consequently, you no longer
must include signals in the top level of your transceiver PHY to determine the status
of the serial Rx and Tx interfaces. Using standard interfaces to access this
device-dependent information should ease future migrations to other device families
and reduce the overall design complexity. However, to facilitate debugging, you may
still choose to include some device-dependent signals in the top level of your design
during the initial simulations or even permanently. All protocol-specific PHY IP in
Stratix V devices also include embedded controls for post-reset initialization, and
reconfiguration, which are available through the Avalon-MM interface.
This chapter enumerates the differences between the ALTGX megafunction for use
with Stratix IV GX devices and the protocol-specific transceiver PHYs for use with
Stratix V GX devices in the current release. The following devices are included:
■ XAUI PHY
■ PCI Express PHY (PIPE)
■ Custom PHY
XAUI PHY
This section lists the differences between the parameters and signals for the XAUI
PHY IP core and the ALTGX megafunction when configured in the XAUI functional
mode.
Parameter Differences
Table 10–1 lists the XAUI PHY parameters and the corresponding ALTGX
megafunction parameters.
Table 10–1. Comparison ALTGX Megafunction and XAUI PHY Parameters (Part 1 of 2)
ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name Comments
Number of channels Number of XAUI interfaces
In Stratix V devices, this
parameter is locked to 1 (for
4 channels). You cannot
change it in the current
release.
Train receiver clock and data recover (CDR) from
pll_inclk (On)
Not available as parameters in
the MegaWizard interface
Use assignment editor to
make these assignmentTx PLL bandwidth mode (Auto)
Rx CDR bandwidth mode (Auto)