User guide

10–4 Chapter 10: Migrating from Stratix IV to Stratix V
PCI Express PHY (PIPE)
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
PCI Express PHY (PIPE)
This section lists the differences between the parameters and signals for the PCI
Express PHY (PIPE) IP core and the ALTGX megafunction when configured in the
PCI Express (PIPE) functional mode.
Parameter Differences
Table 10–3 lists the PCI Express PHY (PIPE) parameters and the corresponding
ALTGX megafunction parameters.
Transceiver Reconfiguration
reconfig_clk 1 Not available —
reconfig_togxb [3:0] Not available —
reconfig_fromgxb [16:0] Not available —
Avalon MM Management Interface
Not available
phy_mgmt_clk_rst 1
phy_mgmt_clk 1
phy_mgmt_address [8:0]
phy_mgmt_read 1
phy_mgmt_readdata [31:0]
phy_mgmt_write 1
phy_mgmt_writedata [31:0]
Note to Table 10–2:
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
Table 10–2. Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals (Part 3 of 3) (Note 1)
Stratix IV GX Devices Stratix V Devices
Signal Name Width Signal Name Width
Table 10–3. Comparison of ALTGX Megafunction and PCI Express PHY (PIPE) Parameters (Part 1 of 2)
ALTGX Parameter Name (Default Value) PCI Express PHY (PIPE) Parameter Name Comments
Number of channels Number of Lanes
Channel width Deserialization factor
Subprotocol Protocol Version
input clock frequency PLL reference clock frequency
Starting Channel Number —
Automatically set to 0.
Quartus II software handles
lane assignments.
Enable low latency sync
pipe_low_latency_syncronous_mode
Enable RLV with run length of pipe_run_length_violation_checking Always on
Enable electrical idle inference
functionality
Enable electrical idle inferencing
—
phy_mgmt_clk_in_mhz
For embedded reset
controller to calculate delays