User guide

10–6 Chapter 10: Migrating from Stratix IV to Stratix V
PCI Express PHY (PIPE)
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
pll_powerdown
Refer to the “Avalon-MM PHY Management
Interface” on page 6–6 and “PCI Express PHY
(PIPE) IP Core Registers” on page 6–6
1
rx_analogreset 1
rx_digitalreset 1
tx_digitalreset 1
gxb_powerdown 1
cal_blk_powerdown 1
Not available
tx_ready (reset control status) 1
Not available
rx_ready (reset curl status) 1
PIPE interface Ports
tx_datain pipe_txdata [ <n><d> -1:0]
tx_ctrlenable pipe_txdatak [( <d> /8)* <n> -1:0]
tx_detectrxloop pipe_txdetectrx_loopback [ <n> -1:0]
tx_forcedispcompliance pipe_txcompliance [ <n> -1:0]
tx_forceelecidle pipe_txelecidle
[ <n> -1:0]
txswing pipe_txswing
[ <n> -1:0]
tx_pipedeemph[0] pipe_txdeemph
[ <n> -1:0]
tx_pipemargin[2:0] pipe_txmargin [3 <n> -1:0]
rateswitch[0] pipe_rate[1:0] [ <n> -1:0]
powerdn pipe_powerdown [2 <n> -1:0]
rx_elecidleinfersel pipe_eidleinfersel [3 <n> -1:0]
rx_dataout pipe_rxdata [ <n> -* <d> -1:0]
rx_ctrldetect pipe_rxdatak [( <d> /8)* <n> -1:0]
pipedatavalid pipe_rxvalid [ <n> -1:0]
pipe8b10binvpolarity pipe_rxpolarity [ <n> -1:0]
pipeelecidle pipe_rxelecidle [ <n> -1:0]
pipephydonestatus pipe_phystatus [ <n> -1:0]
pipestatus pipe_rxstatus [3 <n> -1:0]
Non-PIPE ports
rx_pll_locked rx_is_lockedtoref [ <n> --1:0]
rx_freqlocked rx_is_lockedtodata [ <n> --1:0]
pll_locked pll_locked 1
rx_syncstatus
rx_syncstatus (also management
interface)
[( <d> /8)* <n> -1:0]
Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 2 of 3)
(Note 1)
Stratix IV GX Device Signal Name Stratix V Device Signal Name Width