User guide

Chapter 10: Migrating from Stratix IV to Stratix V 10–7
PCI Express PHY (PIPE)
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
rx_locktodata
Refer to the “Avalon-MM PHY Management
Interface” on page 6–6
[
<n> -1:0]
rx_locktorefclk [ <n> -1:0]
tx_invpolarity [ <n> -1:0]
rx_errdetect [( <d> /8)* <n> -1:0]
rx_disperr [( <d> /8)* <n> -1:0]
rx_patterndetect [( <d> /8)* <n> -1:0]
tx_phase_comp_fifo_error [ <n> -1:0]
rx_phase_comp_fifo_error [ <n> -1:0]
rx_signaldetect [ <n> -1:0]
rx_rlv [ <n> -1:0]
rx_datain rx_serial_data [ <n> -1:0]
tx_dataout tx_serial_data [ <n> -1:0]
cal_blk_clk cal_blk_clk 1
fixedclk fixedclk 1
Reconfiguration
reconfig_clk
Refer to the “Avalon-MM PHY Management
Interface” on page 6–6
1
reconfig_togxb [3:0]
reconfig_fromgxb [16:0]
Avalon MM Management Interface
Not available
phy_mgmt_clk_reset 1
phy_mgmt_clk 1
phy_mgmt_address [8:0]
phy_mgmt_read 1
phy_mgmt_readdata [31:0]
phy_mgmt_write 1
phy_mgmt_writedata [31:0]
Note to Table 10–4:
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 3 of 3)
(Note 1)
Stratix IV GX Device Signal Name Stratix V Device Signal Name Width