User guide

Chapter 10: Migrating from Stratix IV to Stratix V 10–9
Custom PHY
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Port Differences
Table 10–4 lists the differences between the top-level signals in Stratix IV GX and
Stratix V GX/GS devices.
Table 10–6. Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals
ALTGX Custom PHY Width
Avalon MM Management Interface
Not available
phy_mgmt_clk_reset 1
phy_mgmt_clk 1
phy_mgmt_address 8
phy_mgmt_read 1
phy_mgmt_readdata 32
phy_mgmt_write 1
phy_mgmt_writedata 32
Clocks
pll_inclk pll_ref_clk [<p>-1:0]
Avalon-ST Tx Interface
tx_datain tx_parallel_data [<d><n>-1:0]
tx_ctrlenable tx_datak [<d><n>-1:0]
rx_ctrldetect rx_datak [<d><n>-1:0]
Avalon-ST Rx Interface
rx_dataout rx_parallel_data [<d><n>-1:0]
rx_runningdisp rx_runningdisp [<d/8><n>-1:0]
rx_enabyteord rx_enabyteord [<n>-1:0]
High Speed Serial I/O
rx_datain rx_serial_data [<n>-1:0]
tx_dataout tx_serial_data [<n>-1:0]
rx_freqlocked rx_is_lockedtodata [<n>-1:0]
Note to Table 10–6:
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.