User guide

Chapter 1: Introduction 1–7
Reset Controller
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
3. Finally, rx_ready is asserted and phy_ mgmt_clk_reset goes low, ending the reset
state.
\
Figure 1–5 shows the hardware modules and internal signals that implement reset in
Stratix V devices.
f For additional timing diagrams illustrating resets for many configurations, refer to
Reset Control and Power Down in volume 4 of the Stratix IV Device Handbook for
Stratix IV devices or Reset Control and Power Down in volume 2 of the Stratix V Device
Handbook for Stratix V devices.
Figure 1–4. Reset Sequence
phy_mgmt_clk
phy_mgmt_clk_reset
pll_islocked
rx_oc_busy
rx_islocked_toref
powerdown_all
tx_ready
rx_ready
Figure 1–5. Block Diagram of the Reset Sequence Controller
S
tx_pll_is_locked
rx_digitalreset
pll_powerdown
phy_mgmt_clk_reset
tx_ready
rx_ready
Transceiver PHY
rx_analogresettx_digitalreset
rx_is_lockedtodata
Avalon-MM
Interface
to / from
user logic
Receiver
PMA
CDR
Transmitter
PCS
Transmitter
PMA
Transmitter
PLL
Receiver
PCS
Reset Controller
Avalon - MM
PHY Management
Dynamic
Reconfiguration
PCS and PMA Control
and Status Register
Memory Map
SMS