User guide
1–8 Chapter 1: Introduction
Avalon-MM PHY Management
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Avalon-MM PHY Management
You can use the Avalon-MM PHY Management module to read and write the control
and status registers in the PCS and PMA. This module includes both Avalon-MM
master and slave ports and acts as a bridge. It transfers commands received from an
embedded controller on its slave port to its master port. The Avalon-MM PHY
management master interface connects the Avalon-MM slave ports of PCS and PMA
registers and the Transceiver Reconfiguration module, allowing you to manage these
Avalon-MM slave components through a simple, standard interface. (Refer to
Figure 1–1 on page 1–2.)
Serial Loopback
All of the PHYs, with the exception of PCI Express, support serial loopback mode in
both Stratix IV and Stratix V devices. PCI Express supports reverse parallel loopback
mode as required by the PCI Express Base Specification. Figure 1–6 shows the datapath
for serial loopback. The data from the FPGA fabric passes through the TX channel and
is looped back to the RX channel, bypassing the RX buffer. The received data is
available to the FPGA logic for verification. Using the serial loopback option, you can
check the operation of all enabled PCS and PMA functional blocks in the TX and RX
channels. When serial loopback is enabled, the TX channel sends the data to both the
tx_serial_data
output port and the RX channel.
Unsupported Features
The protocol-specific PHYs are not supported in SOPC Builder in the current release.
Figure 1–6. Serial Loopback
Tx PCS
Rx PCS
FPGA
Fabric
Tx PMA
tx_dataout
Serializer
Rx PMA
Serial
loopback
De-
serializer
To FPGA fabric
for verication
Transceiver