User guide

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
3. 10GBASE-R PHY IP Core
The Altera 10GBASE-R PHY IP core implements the functionality described in IEEE
802.3 Clause 49. It delivers serialized data to an optical module that drives multi-mode
optical fiber at a line rate of 10.3125 Gbps. In a multi-channel implementation of
10GBASE-R, each channel of the 10GBASE-R PHY IP core operates independently.
You can instantiate multiple channels to achieve higher bandwidths. The PCS is
available in soft logic for Stratix IV GT devices; it connects to a separately instantiated
hard PMA.
Figure 3–1 illustrates a multiple 10 GbE channel IP core in a Stratix IV GT device.
In this configuration, 10GBASE-R PHY IP core includes a soft PCS and a hard PMA.
The soft PCS connects to an Ethernet MAC running at 156.25 Mbps and transmits data
to a hard 10 Gbps transceiver PMA running at 10.3125 Gbps in a Stratix IV GT device.
Figure 3–1. Complete 10GBASE-R PHY Design
To MAC
To Embedded
Controller
Avalon-MM
connections
10GBase-R PHY
SDR XGMII
72 bits @ 156.25 Mbps
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
PHY
Management
Bridge
M
S
S
Low Latency
Controller
S
Transceiver
Reconfig
Controller
Alt_PMA
10GBASE-R
10.3 Gbps
ALTGX<0>
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S
Alt_PMA
10GBASE-R
10.3 Gbps
ALTGX<n>
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S