User guide

3–2 Chapter 3: 10GBASE-R PHY IP Core
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
To make most effective use of this soft PCS and hard PMA configuration, you can
group up to four channels in a single quad and control their functionality using one
Avalon-MM PHY management bridge, transceiver reconfiguration module, and low
latency controller. As Figure 3–1 illustrates, the Avalon-MM bridge Avalon-MM
master port connects to the Avalon-MM slave port of the transceiver reconfiguration
and low latency controller modules so that you can update analog settings using the
standard Avalon-MM interface.
1 This configuration does not require all four channels in a quad run the 10GBASE-R
protocol.
Figure 3–2 shows the 10GBASE-R PHY IP core available for Stratix V devices. Both the
PCS and PMA of the 10GBASE-R PHY are available as hard IP blocks in Stratix V,
devices saving FPGA resources.
f For a 10-Gbps Ethernet solution that includes both the Ethernet MAC and the
10GBASE-R PHY, refer to the 10-Gbps Ethernet MAC MegaCore Function User Guide.
f For more detailed information about the 10GBASE-R transceiver channel datapath,
clocking, and channel placement, refer to the “10GBASE-R” section in the Transceiver
Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Figure 3–2. 10GBASE-R PHY with Hard PCS with Hard PMA in Stratix V Devices
10GBASE-R PHY IP Core
10/3125 Gbps serial
XFI/SFI
Networ
Interfac
Stratix V FPGA
Hard PMA
PMD
Copper
or
Optical
Hard PCS
10GBASE-R
64b/66b
Scrambler
PRBS
Gearbox
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
Control & Status