User guide

Chapter 3: 10GBASE-R PHY IP Core 3–5
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Interfaces
Figure 3–3 illustrates the top-level signals of the 10Base-R PHY.
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the Hardware Component Description File (_hw.tcl).
f For more information about _hw.tcl files, refer to the Component Interface Tcl Reference
chapter in the SOPC Builder User Guide.
The following sections describe the signals in each interface.
Figure 3–3. 10GBASE-R PHY Pinout Showing Interfaces for Both Internal and External Transceivers
f
xgmii_tx_dc <n> [71:0]
tx_ready
xgmii_tx_clk
xgmii_rx_dc
<n> [71:0]
rx_ready
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_addr[15:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
10GBASE-R Top-Level Signals
Clock
Signals for
External PMA an
d
Reconfiguration
Stratix IV only
rx_serial_data <n>
tx_serial_data <n>
gxb_pdn
pll_locked
pll_pdn
cal_blk_pdn
rx_oc_busy
cal_blk_clk
reconfig_to_gxb[3:0]
reconfig_from_gxb[16:0]
rx_block_lock
rx_hi_ber
pll_ref_clk
Transceiver
Serial Data
SDR XGMII Tx
Inputs from MAC
SDR XGMII Rx
Outputs from PCS
to MAC
Avalon-MM PHY
Management
Interface
Status