User guide

3–8 Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Avalon-MM Interface
The Avalon-MM module provides access to the PCS and PMA registers, the
Transceiver Reconfiguration IP core, and the Low Latency PHY Controller IP core.
PHY management block includes Avalon-MM master and slave interfaces and acts as
a bridge. It transfers commands received on its Avalon-MM slave interface to its
Avalon-MM port.
Table 3–9 describes the signals that comprise the Avalon-MM PHY Management
interface.
f Refer to the “Typical Slave Read and Write Transfers” and “Master Transfers” sections in
the “Avalon Memory-Mapped Interfaces” chapter of the Avalon Interface Specifications for
timing diagrams.
xgmii_rx_dc[17] xgmii_sdr_ctrl[1] Lane 1 control
xgmii_rx_dc[25:18] xgmii_sdr_data[23:16] Lane 2 data
xgmii_rx_dc[26] xgmii_sdr_ctrl[2] Lane 2 control
xgmii_rx_dc[34:27] xgmii_sdr_data[31:24] Lane 3 data
xgmii_rx_dc[35] xgmii_sdr_ctrl[3] Lane 3 control
xgmii_rx_dc[43:36] xgmii_sdr_data[39:32] Lane 4 data
xgmii_rx_dc[44] xgmii_sdr_ctrl[4] Lane 4 control
xgmii_rx_dc[52:45] xgmii_sdr_data[47:40] Lane 5 data
xgmii_rx_dc[53] xgmii_sdr_ctrl[5] Lane 5 control
xgmii_rx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 data
xgmii_rx_dc[62] xgmii_sdr_ctrl[6] Lane 6 control
xgmii_rx_dc[70:63] xgmii_sdr_data[63:56] Lane 7 data
xgmii_rx_dc[71] xgmii_sdr_ctrl[7] Lane 7 control
Table 3–8. Mapping from XGMII RX Bus to the XGMII SDR Bus (Part 2 of 2)
Signal Name XGMII Signal Name Description
Table 3–9. Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input
The clock signal that controls the Avalon-MM PHY management,
calibration, and reconfiguration interfaces. For Stratix IV devices, the
maximum frequency is 50 MHz.
phy_mgmt_clk_reset Input
Global reset signal that resets the entire 10GBASE-R PHY. A positive
edge on this signal triggers the reset controller.
phy_mgmt_addr[8:0] Input 9-bit Avalon-MM address. Refer to for the address fields.
phy_mgmt_writedata[31:0] Input Input data.
phy_mgmt_readdata[31:0] Output Output data.
phy_mgmt_write Input Write signal. Asserted high.
phy_mgmt_read Input Read signal. Asserted high.
phy_mgmt_waitrequest Output
When asserted, indicates that the Avalon-MM slave interface is unable
to respond to a read or write request. When asserted, control signals
to the Avalon-MM slave interface must remain constant.