User guide

3–10 Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
PMA Channel Control and Status
0x061 [31:0] RW
pma _ serial _ loopback
Writing a 1 to channel <n> puts channel <n> in serial
loopback mode.
0x063 [31:0] R
pma_rx_signaldetect
When asserted, the signal level circuit senses if the
specified voltage level exists at the receiver input buffer. Bit
<n> corresponds to channel <n>.
0x064 [31:0] RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
0x066 [31:0] R
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode. Bit <n> corresponds to channel <n>.
0x067 [31:0] R
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR PLL is locked to
the reference clock. Bit <n> corresponds to channel <n>.
10GBASE-R PCS–Stratix IV Devices
0x080 [31:0] RW
INDIRECT_ADDR
Provides for indirect addressing of all PCS control and
status registers. Use this register to specify the logical
channel address of the PCS channel you want to access.
0x081
[2] RW
RCLR_ERRBLK_CNT
When set to 1, clears the error block count register.
To block: Block synchronizer
[3] RW
RCLR_BER_COUNT
When set to 1, clears the bit error rate (BER) register.
To block: BER monitor
0x082
[0] R
PCS_STATUS When asserted indicates that the PCS link is up.
[1] R
HI_BER
When asserted by the BER monitor block, indicates that the
PCS is recording a high BER.
From block: BER monitor
[2] R
BLOCK_LOCK
When asserted by the block synchronizer, indicates that the
PCS is locked to received blocks.
From Block: Block synchronizer
[3] R
TX_FIFO_FULL
When asserted, indicates the TX FIFO is full.
From block: TX FIFO
[4] R
RX_FIFO_FULL
When asserted, indicates the RX FIFO is full.
From block: RX FIFO
[5] R
RX_SYNC_HEAD_ERROR
When asserted, indicates an RX synchronization error. This
signal is Stratix V devices only.
[6] R
RX_SCRAMBLER_ERROR
When asserted, indicates an RX scrambler error. This signal
is Stratix V devices only.
Table 3–10. 10GBASE-R Register Descriptions (Part 2 of 3)
Word
Addr
Bit R/W Name Description