User guide

Chapter 3: 10GBASE-R PHY IP Core 3–11
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Status Interface
Table 3–11 describes signals that provide status information.
Clocks, Reset, and Powerdown
The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY. A
positive edge on this signal triggers a reset.
Refer to the Reset Control and Power Down chapter in volume 2 of the Stratix IV Device
Handbook for additional information about reset sequences in Stratix IV devices.
0x083
[5:0] R
BER_COUNT
Records the bit error rate (BER). Not available for Stratix V
devices.
From block: BER monitor
[7:0] R
ERROR_BLOCK_COUNT
Records the number of blocks that contain errors. Not
available for Stratix V devices.
From Block: Block synchronizer
Table 3–10. 10GBASE-R Register Descriptions (Part 3 of 3)
Word
Addr
Bit R/W Name Description
Table 3–11. Status Outputs
Signal Name Direction Description
block_lock Output Asserted to indicate that the block synchronizer has established synchronization.
hi_ber Output Asserted by the BER monitor block to indicate a high bit error rate.