User guide

3–12 Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
When connected to the hard PMA, the PCS runs at 257.8125 MHz using the
pma_rx_clock provided by the PMA. You must provide the PMA a input reference
clock running at 644.53725MHz to generate the 257.8125 MHz clock. Figure 3–4
illustrates the clock generation and distribution for Stratix IV devices.
Figure 3–4. Stratix IV GT Clock Generation and Distribution
pll_ref_clk
644.53125 MHz
10.3125
Gbps serial
516.625
MHz
257.8125
MHz
516.625
MHz
257.8125
MHz
156.25 MHz
10GBASE-R Transceiver Channel - Stratix IV GT
TX
RX
TX PCS
(hard IP)
TX PCS
(soft IP)
204064
TX PMA
/2
10.3125
Gbps serial
RX PCS
(hard IP)
RX PCS
(soft IP)
20
40
64
RX PMA
/2
5/4
TX PLL
8/33
GPLL
xgmii_rx_clk
xgmii_tx_clk