User guide

3–14 Chapter 3: 10GBASE-R PHY IP Core
TimeQuest Timing Constraints
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Serial Interface
Table 3–13 describes the input and outputs of the transceiver.
External PMA Control and Reconfig Interface
Table 3–14 describes the additional top-level signals 10GBASE-R PHY IP core when
the configuration includes external modules for PMA control and reconfiguration.
You enable this configuration by turning on Use external PMA control and reconfig
available for Stratix IV GT devices. This configuration is illlustrated in Figure 3–1 on
page 3–1.
TimeQuest Timing Constraints
The timing constraints for Stratix IV GX designs are in alt_10gbaser_phy.sdc. If your
design does not meet timing with these constraints, use LogicLock
TM
for the
alt_10gbaser_pcs block. You can also apply LogicLock to the alt_10gbaser_pcs and
slightly expand the lock region to meet timing.
h For more information about LogicLock, refer to About LogicLock Regions in Quartus II
Help.
Table 3–13. Transceiver Serial Interface (Note 1)
Signal Name Direction Description
rx_serial_data<n>
Input Receiver input data
tx_serial_data<n>
Output Transmitter output data
Note to Table 3–13:
(1) <n> is the channel number
Table 3–14. External PMA and Reconfiguration Signals
Signal Name Direction Description
gxb_pdn
Input When asserted, powers down the entire GX block. Active high.
pll_locked
Output When asserted, indicates that the PLL is locked. Active high.
pll_pdn
Input When asserted, powers down the TX PLL. Active high.
cal_blk_pdn
Input When asserted, powers down the calibration block. Active high.
rx_oc_busy
Output
When asserted, indicates offset cancellation is in progress. The
transceiver must remain in reset until offset cancellation completes.
Active high.
cal_blk_clk
Input
Calibration clock. For Stratix IV devices only. It must be in the range
37.5–50 MHz. You can use the same clock for the phy_mgmt_clk and
the
cal_blk_clk .
reconfig_to_gxb[3:0]
Input
Reconfiguration signals from the transceiver reconfiguration controller
to the PHY device. This signal is only available in Stratix IV devices.
reconfig_from_gxb[16:0]
Output
Reconfiguration RAM. The PHY device drives this RAM data to the
transceiver reconfiguration IP.