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Chapter 3: 10GBASE-R PHY IP Core 3–15

TimeQuest Timing Constraints

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide

Example 3–1 provides the Synopsys Design Constraints File (.sdc) timing constraints

for the 10GBASE-R IP core. To pass timing analysis, you must decouple the clocks in

different time domains. Be sure to verify the each clock domain is correctly buffered in

the top level of your design. You can find the .sdc file in your top-level working

directory. This is the same directory that includes your top-level .v or .vhd file.

Example 3–1. Synopsys Design Constraints for Clocks

#**************************************************************

# Timing Information

#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************

# Create Clocks

#**************************************************************

create_clock -name {xgmii_tx_clk} -period 6.400 -waveform { 0.000 3.200 } [get_ports

{xgmii_tx_clk}]

create_clock -name {phy_mgmt_clk} -period 20.00 -waveform { 0.000 10.000 } [get_ports

{phy_mgmt_clk}]

create_clock -name {pll_ref_clk} -period 1.552 -waveform { 0.000 0.776 } [get_ports

{ref_clk}]

#derive_pll_clocks

derive_pll_clocks -create_base_clocks

#derive_clocks -period "1.0"

#**************************************************************

# Create Generated Clocks

#**************************************************************

create_generated_clock -name pll_mac_clk -source [get_pins -compatibility_mode

{*altpll_component|auto_generated|pll1|clk[0]}]

create_generated_clock -name pma_tx_clk -source [get_pins -compatibility_mode

{*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}]

**************************************************************

## Set Clock Latency

#**************************************************************

# Set Clock Uncertainty

#**************************************************************

derive_clock_uncertainty

set_clock_uncertainty -from [get_clocks

{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -to pll_ref_clk -setup 0.1

set_clock_uncertainty -from [get_clocks

{*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -setup

0.08

set_clock_uncertainty -from [get_clocks

{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -to pll_ref_clk -hold 0.1

set_clock_uncertainty -from [get_clocks

{*siv_alt_pma|pma_direct|auto_generated|transmit_pcs0|clkout}] -to pll_ref_clk -hold

0.08

#**************************************************************

# Set Input Delay

#**************************************************************

# Set Output Delay

#**************************************************************

# Set Clock Groups

#**************************************************************

set_clock_groups -exclusive -group phy_mgmt_clk -group xgmii_tx_clk -group [get_clocks

{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}] -group [get_clocks

{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -group [get_clocks

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]}]