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3–16 Chapter 3: 10GBASE-R PHY IP Core

TimeQuest Timing Constraints

Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

1 This .sdc file is only applicable to the 10GBASE-R PHY IP core when compiled in

isolation. You can use it as a reference to help in creating your own .sdc file.

Synopsys Design Constraints for Clocks (continued)

##**************************************************************

# Set False Path

#**************************************************************

set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|rx_pma_rstn} -to [get_clocks

{{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk

xgmii_tx_clk}]

set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|rx_usr_rstn} -to [get_clocks

{{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk

xgmii_tx_clk}]

set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|tx_pma_rstn} -to [get_clocks

{{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}

{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk

xgmii_tx_clk}]

set_false_path -from {*siv_10gbaser_xcvr*clk_reset_ctrl|tx_usr_rstn} -to [get_clocks

{{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}

{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk

xgmii_tx_clk}]

set_false_path -from {*siv_10gbaser_xcvr*rx_analog_rst_lego|rinit} -to [get_clocks

{{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}

{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk

xgmii_tx_clk}]

set_false_path -from {*siv_10gbaser_xcvr*rx_digital_rst_lego|rinit} -to [get_clocks

{{*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}

{*siv_alt_pma|pma_ch*.pma_direct|transmit_pcs*|clkout}

{*pll_siv_xgmii_clk|altpll_component|auto_generated|pll1|clk[0]} phy_mgmt_clk

xgmii_tx_clk}]

#**************************************************************

# Set Multicycle Paths

#**************************************************************

#**************************************************************

# Set Maximum Delay

#**************************************************************

#**************************************************************

# Set Minimum Delay

#**************************************************************

#**************************************************************

# Set Input Transition

#**************************************************************