User guide

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
4. XAUI PHY IP Core
The Altera XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to
extend the operational distance of the XGMII interface and reduce the number of
interface signals. XAUI extends the physical separation possible between the 10 Gbps
Ethernet MAC function implemented in an Altera FPGA and the Ethernet standard
PHY component on a PCB to one meter.
Figure 4–1 illustrates the top-level blocks of the XAUI PHY for Stratix IV GX or
Stratix V devices.
For Stratix IV GX and GT devices, you can choose a hard XAUI physical coding
sublayer (PCS) and physical media attachment (PMA), or a soft XAUI PCS and PMA
in low latency mode. You can also combine both hard and soft PCS configurations in
the same device, using all six channels in a transceiver bank. In Quartus II version
10.1, the PCS is only available in soft logic for Stratix V devices.
f For more detailed information about the XAUI transceiver channel datapath,
clocking, and channel placement, refer to the “XAUI” section in the Transceiver
Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Release Information
Table 4–1 provides information about this release of the XAUI PHY IP core.
Figure 4–1. XAUI PHY with Hard IP PCS and PMA in Stratix IV GX or Stratix V Devices
XAUI IP Core
4 x 3.125 Gbps serial
Arria II GX, Cyclone IV GX, Stratix IV GX or GT, or Stratix V FPGA
Hard PMA
PCS
8B/10B
Word Aligner
Phase Comp
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
Control & Status
4
4
Table 4–1. XAUI Release Information (Part 1 of 2)
Item Description
Version 10.1
Release Date December 2010
Ordering Codes (Note 1)
IP-XAUIPCI (primary)–soft PCS
IPR-XAUIPCS (renewal)–soft PCS
Product ID 00D7