User guide

Chapter 4: XAUI PHY IP Core 4–3
Parameter Settings
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Parameter Settings
To configure the XAUI IP core in the parameter editor, click Installed Plug-Ins >
Interfaces >Ethernet> XAUI PHY v10.1.
This section describes the XAUI PHY IP core parameters, which you can set using the
parameter editor. Table 4–4 lists the settings available on General Options tab.
Table 4–5 describes the settings available on the Additional Options tab.
Table 4–4. General Options
Name Value Description
Device family
Arria II GX
Cyclone IV GX
Stratix IV
Stratix V
The target device family.
Starting channel number 0–124
The physical starting channel number in the Altera device for channel
0 of this XAUI PHY. In Arria II GX, Cyclone IVGX, and Stratix IV
devices, this starting channel number must be 0 or a multiple of 4.
There are no numbering restrictions for Stratix V devices.
Assignment of the starting channel number is needed for serial
transceiver dynamic reconfiguration.
XAUI interface type
Hard XAUI
Soft XAUI
Specifies whether the interface is implemented in soft or hard logic.
Each interface includes 4 channels.
Number of XAUI interfaces 1
Specifies the number of XAUI interfaces. Only 1 is available in the
current release.
Table 4–5. Advanced Options—Stratix IV
Name Value Description
Soft XAUI PLL type
CMU PLL
ATX PLL
Allows you to choose a clock multiplier unit (CMU) or auxiliary
transmit (ATX) PLL. The CMU PLL is designed to achieve low TX
channel-to-channel skew. The ATX PLL is designed to improve jitter
performance. This option is only available for the soft PCS.
Include control and status portsOn/Off
If you turn this option on, the top-level IP core include the status
signals and digital resets shown in Figure 4–3 on page 4–5 and
Figure 4–4 on page 4–6. If you turn this option off, you can access
control and status information using Avalon-MM interface to the
control and status registers. The default setting is off.
External PMA control and
configuration
On/Off
If you turn this option on, the PMA signals are brought up to the top
level of the XAUI IP core. This option is useful if your design
includes multiple instantiations of the XAUI PHY IP core. To save
FPGA resources, you can instantiate the Low Latency PHY Controller
and Transceiver Reconfiguration Controller IP cores separately in
your design to avoid having these IP cores instantiated in each
instance of the XAUI PHY IP core.
If you turn this option off, the PMA signals remain internal to the
core. The default setting is off. This option is only available for
Arria II GX and Stratix IV GX devices.
Advanced Options—Arria II GX, Cyclone IV GX, a Stratix V Devices
Include control and status portsOn/Off
If you turn this option on, the top-level IP core includes the TX and
RX status signals shown in Figure 4–3 on page 4–5.