User guide

4–4 Chapter 4: XAUI PHY IP Core
Configurations
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
For a description of the PMA analog options, refer to “PMA Analog Options” on
page 8–4.
Configurations
Figure 4–2 illustrates one configuration of the XAUI IP core. As this figure illustrates,
if your variant includes a single instantiation of the XAUI IP core, the transceiver
reconfiguration control logic is included in the XAUI PHY IP core.
For more information about transceiver reconfiguration, refer to Chapter 9,
Transceiver Reconfiguration Controller.
Figure 4–2. XAUI PHY Using One Channel Low Latency PHY Controller
System
Interconnect
Fabric
System
Interconnect
Fabric
Inter-
leave
PCS
S
Alt_PMA
S
S
Low Latency
Controller
S
Transceiver
Reconfiguration
Controller
Transceiver Quad 0
Hard XAUI PHY
4 x 3.125 Gbps serial
4
4
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
M
Avalon-MM
PHY
Mgmt
S
PMA Channel
Controller