User guide

Chapter 4: XAUI PHY IP Core 4–5
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Interfaces
Figure 4–3 illustrates the top-level signals of the XAUI PHY IP core for the soft IP
implementation which is available for Stratix IV GX and Stratix V devices. Figure 4–4
illustrates the top-level signals of the XAUI PHY IP core for the hard IP
implementation which is available for Stratix IV GX devices. With the exception of the
optional signals available for debugging, the pinout of the two implementations is
nearly identical.
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used to
define component interfaces in the _hw.tcl.
f For more information about _hw.tcl files refer to refer to the Component Interface Tcl
Reference chapter in the SOPC Builder User Guide.
Figure 4–3. XAUI Top-Level Signals—Soft PCS and Hard PMA
xgmii_tx_dc[71:0]
xgmii_tx_clk
xmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
rx_digitalreset
tx_digitalreset
XAUI Top-Level Signals Soft IP Implementation
Rx Status
Optional
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_channelaligned
rx_disperr[7:0]
rx_errdetect[7:0]
rx_syncstatus[7:0]
cal_blk_powerdown
gxb_powerdown
pll_powerdown
pll_locked
reconfig_fromgxb[67:0]
reconfig_togxb[3:0]
rx_ready
tx_ready
Transceiver
Serial Data
SDR Tx XGMII
SDR Rx XGMII
Avalon-MM PHY
Management
Interface
Clocks
and
Reset
Optional
Optional
PMA
Channel
Controlle
r