User guide

4–6 Chapter 4: XAUI PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Figure 4–4 illustrates the top-level signals of the XAUI PHY IP core for the hard IP
implementation which is available for Arria II GX, Cyclone IV GX, and Stratix IV GX
devices.
The following sections describe the signals in each interface.
SDR XGMII TX Interface
The XAUI PCS interface to the FPGA fabric uses a single data rate (SDR) XGMII
interface. This interface implements a simple version of Avalon-ST protocol. The
interface does not include ready or valid signals; consequently, the sources always
drive data and the sinks must always be ready to receive data.
f For more information about the Avalon-ST protocol, including timing diagrams, refer
to the Avalon Interface Specifications.
Figure 4–4. XAUI Top-Level Signals–Hard IP PCS and PMA
Note to Figure4–3:
(1) reconfig_fromgxb[67:17] is terminated to ground internally.
xgmii_tx_dc[71:0]
xgmii_tx_clk
xmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
rx_analogreset
rx_digitalreset
tx_digitalreset
XAUI Top-Level Signals Hard IP Implementation
PMA
Channel
Controller
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_invpolarity[3:0]
rx_set_locktodata[3:0]
rx_is_lockedtodata[3:0]
rx_set_locktoref[3:0]
rx_is_lockedtoref[3”0]
tx_invpolarity[3:0]
rx_seriallpbken[3:0]
rx_channelaligned[3:0]
pll_locked
rx_rmfifoempty[3:0]
rx_rmfifofull[3:0]
rx_disperr[7:0]
rx_errdetect[7:0]
rx_patterndetect[7:0]
rx_rmfifodatadeleted[7:0]
rx_rmfifodatainserted[7:0]
rx_runningdisp[7:0]
rx_syncstatus[7:0]
rx_phase_comp_fifo_error[3:0]
tx_phase_comp_fifo_error[3:0]
rx_rlv[3:0]
reconfig_togxb[3:0]
reconfig_fromgxb[67:0]
cal_blk_powerdown
gxb_powerdown
pll_powerdown
pll_locked
rx_ready
tx_ready
Transceiver
Serial Data
Rx and Tx
Status
All Optional
SDR Tx XGMII
SDR Rx XGMII
Avalon-MM PHY
Management
Interface
Clock
and
Reset
Optional
Resets
Transceiver
Reconfiguration
Optional
Note (1)