User guide

Chapter 4: XAUI PHY IP Core 4–7

Interfaces

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide

This interface runs at 156.25 MHz in accordance with XGMII specification; however,

data is only driven on the rising edge of clock. To meet the bandwidth requirements,

the datapath is eight bytes wide with eight control bits, instead of the standard four

bytes of data and four bits of control. The XAUI IP core treats the datapath as two,

32-bit data buses and includes logic to interleave them, starting with the low-order

bytes. Figure 4–5 illustrates the mapping.

Table 4–6 describes the signals in the SDR TX XGMII interface.

SDR XGMII RX Interface

Table 4–6 describes the signals in the SDR RX XGMII interface.

Figure 4–5. Interleaved SDR XGMII Data

Interleaved Result

Original XGMII Data

[63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]

[63:56] [31:24] [55:48] [23:16] [47:40] [15:8] [39:32] [7:0]

Table 4–6. SDR TX XGMII Interface

Signal Name Direction Description

xgmii_tx_dc[71:0]

Source

Contains 4 lanes of data and control for XGMII. Each lane consists of

16 bits of data and 2 bits of control.

■ Lane 0–[7:0]/[8], [16:9]/[17]

■ Lane 1–[25:18]/[26], [34:27]/[35]

■ Lane 2–[43:36]/[44], [52:45]/[53]

■ Lane 3–[61:54]/[62],[70:63]/[71]

xgmii_tx_clk

Input The XGMII SDR TX clock which runs at 156.25 MHz.

Table 4–7. SDR XGMII Interface

Signal Name Direction Description

xgmii_rx_dc[71:0]

Sink