User guide
4–8 Chapter 4: XAUI PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Avalon-MM Interface
The Avalon-MM PHY management block includes master and slave interfaces. This
component acts as a bridge. It transfers commands received on its Avalon-MM slave
interface to its Avalon-MM port. This interface provides access to the PCS and PMA
registers, the Transceiver Reconfiguration, and the Low Latency PHY Controller IP
cores. Table 4–8 describes the signals that comprise the Avalon-MM PHY
Management interface.
f For more information about the Avalon-MM interface, including timing diagrams,
refer to the Avalon Interface Specifications.
Register Descriptions
Table 4–9 specifies the registers that you can access using the Avalon-MM PHY
management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
Table 4–8. Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input Avalon-MM clock input.
phy_mgmt_clk_reset
Input
Global reset signal that resets the entire XAUI PHY. A positive edge
on this signal triggers the reset controller.
phy_mgmt_addr[8:0]
Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input 32-bit input data.
phy_mgmt_readdata[31:0]
Output 32-bit output data.
phy_mgmt_write
Input Write signal. Asserted high.
phy_mgmt_read
Input Read signal. Asserted high.
phy_mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave interface is
unable to respond to a read or write request. When asserted, control
signals to the Avalon-MM slave interface must remain constant.
Table 4–9. XAUI PHY IP Core Registers (Part 1 of 4)
Word
Addr
Bits R/W Register Name Description
PMA Common Control and Status Registers
0x021 [31:0] RW
cal_blk_powerdown
Writing a 1 to channel <
n
> powers down the calibration
block for channel <
n
>.
0x022 [31:0] R
pma_tx_pll_is_locked
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked
bit per system.
Reset Control Registers
0x041 [31:0] RW
reset_ch_bitmask
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <
n
> can be reset when
<
n
> = 1.