User guide
Chapter 4: XAUI PHY IP Core 4–11
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
0x086
[31:8] — Reserved —
[7:4]
R,
sticky
phase_comp_fifo_error[3:
0]
Indicates a RX phase compensation FIFO overflow or
underrun condition on the corresponding lane. Reading the
value of the
phase_comp_fifo_error
register clears the
bits.
From block: RX phase compensation FIFO.
[3:0]
rlv[3:0]
Indicates a run length violation. Asserted if the number of
consecutive 1s or 0s exceeds the number that was set in the
Runlength check option. Bits 0-3 correspond to lanes 0-3,
respectively. Reading the value of the
RLV
register clears the
bits.
From block: Word aligner.
0x087
[31:16] — Reserved —
[15:8]
R,
sticky
rmfifodatainserted[7:0]
When asserted, indicates that the RX rate match block
inserted a ||R|| column. Goes high for one clock cycle per
inserted ||R|| column. Reading the value of the
rmfifodatainserted
register clears the bits.
From block: Rate match FIFO.
[7:0]
rmfifodatadeleted[7:0]
When asserted, indicates that the rate match block has
deleted an ||R|| column. The flag goes high for one clock
cycle per deleted ||R|| column. There are 2 bits for each
lane. Reading the value of the
rmfifodatadeleted
register clears the bits.
From block: Rate match FIFO.
0x088
[31:8] — Reserved —
[7:4]
R,
sticky
rmfifoempty[3:0]
When asserted, indicates that the rate match FIFO is empty
(5 words). Bits 0-3 correspond to lanes 0-3, respectively.
Reading the value of the
rmfifoempty
register clears the
bits.
From block: Rate match FIFO.
[3:0]
rmfifofull[3:0]
When asserted, indicates that rate match FIFO is full (20
words). Bits 0-3 correspond to lanes 0-3, respectively.
Reading the value of the
rmfifofull
register clears the
bits.
From block: Rate match FIFO.
0x089
[31:3] — Reserved —
[2:0]
R,
sticky
phase_comp_fifo_error[2:
0]
Indicates a TX phase compensation FIFO overflow or
underrun condition on the corresponding lane. Reading the
value of the
phase_comp_fifo_error
register clears the
bits.
From block: TX phase compensation FIFO.
0x08a [0] RW
simulation_flag
Setting this bit to 1 shortens the duration of reset and loss
timer when simulating. Altera recommends that you keep
this bit set during simulation.
Table 4–9. XAUI PHY IP Core Registers (Part 4 of 4)
Word
Addr
Bits R/W Register Name Description