User guide

4–12 Chapter 4: XAUI PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Transceiver Serial Data Interface
Table 4–10 describes the signals in the XAUI transceiver serial data interface. There
are four lanes of serial data for both the TX and RX interfaces. This interface runs at
3.125 GHz. There is no separate clock signal because it is encoded in the data.
Dynamic Reconfiguration Interface
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature. These process variations
result in analog voltages that can be offset from required ranges. Dynamic
reconfiguration compensates for variations due to process, voltage, and temperature.
Table 4–11 describes the signals in the reconfiguration interface. If your XAUI PHY IP
core includes a single transceiver quad, these signals are internal to the core. If your
design uses more than one quad, they are external.
1 Dynamic reconfiguration is only supported for Stratix IV devices in the current
release.
Table 4–10. Serial Data Interface
Signal Name Direction Description
xaui_rx_serial_data[3:0] Input Serial input data.
xaui_tx_serial_data[3:0] Output Serial output data.
Table 4–11. Dynamic Reconfiguration Interface
Signal Name Direction Description
reconfig_togxb_data[3:0] Input
Reconfiguration signals from the Transceiver Reconfiguration IP
core to the XAUI transceiver.
reconfig_fromgxb[67:0] Output
Reconfiguration signals from the XAUI transceiver to the
Transceiver Reconfiguration IP core. For XAUI variants using a
hard PCS and PMA, reconfig_fromgxb[67:17] are terminated
to ground internally. The soft PCS in Stratix IV GX and GT devices
use 68 bits.