User guide

4–14 Chapter 4: XAUI PHY IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
PMA Channel Controller
Table 4–13 describes the signals in this interface.
PMA Control and Status Interface Signals–Soft IP Implementation
(Optional)
Table 4–14 lists the optional PMA control and status signals available in the soft IP
implementation. You can also access the state of these signals using the Avalon-MM
PHY Management interface to read the control and status registers which are detailed
in Table 4–9 on page 4–8. However, in some cases, you may need to know the
instantaneous value of a signal to ensure correct functioning of the XAUI PHY. In such
cases, you can include the required signal in the top-level module of your XAUI PHY
IP core.
Table 4–13. Low Latency PHY Controller
Signal Name Direction Description
cal_blk_powerdown Input
Powers down the calibration block. A high-to-low transition on this
signal restarts calibration. Only available in Arria II GX and
Stratix IV GX, and Stratix IV GT devices.
gxb_powerdown Input
When asserted, powers down the entire transceiver block. Only
available in Arria II GX and Stratix IV GX, and Stratix IV GT devices.
pll_powerdown Input
Powers down the CMU PLL. Only available in Arria II GX and
Stratix IV GX, and Stratix IV GT devices.
pll_locked Output
Indicates CMU PLL is locked. Only available in Arria II GX and
Stratix IV GX, and Stratix IV GT devices.
rx_ready Output Indicates PMA RX has exited the reset state.
tx_ready Output Indicates PMA TX has exited the reset state.
Table 4–14. Optional Control and Status Signals—Soft IP Implementation, Stratix IV GX and Stratix V Devices
Signal Name Direction Description
rx_channelaligned Output When asserted, indicates that all 4 RX channels are aligned.
rx_disperr[7:0]
Output
Received 10-bit code or data group has a disparity error. It is paired
with
rx_errdetect which is also asserted when a disparity error
occurs. The
rx_disperr signal is 2 bits wide per channel for a total
of 8 bits per XAUI link.
rx_errdetect[7:0]
Output
When asserted, indicates an 8B/10B code group violation. It is
asserted if the received 10-bit code group has a code violation or
disparity error. It is used along with the
rx_disperr signal to
differentiate between a code violation error, a disparity error, or
both.The
rx_errdetect signal is 2 bits wide per channel for a total
of 8 bits per XAUI link.
rx_syncstatus[7:0]
Output
Synchronization indication. RX synchronization is indicated on the
rx_syncstatus port of each channel. The rx_syncstatus signal
is 2 bits wide per channel for a total of 8 bits per XAUI link.