User guide

5–2 Chapter 5: Interlaken PHY IP Core
Device Family Support
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
f For more detailed information about the Interlaken transceiver channel datapath,
clocking, and channel placement, refer to the “Interlaken” section in the Transceiver
Protocol Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
■ Preliminary support—Verified with preliminary timing models for this device.
Table 5–1 shows the level of support offered by the Interlaken PHY IP core for Altera
device families
Performance and Resource Utilization
Table 5–2 shows the typical expected device resource utilization for different
configurations using the current version of the Quartus II software targeting a
Stratix V (5SGXMB6R2F45C2) device.
633
Parameter Settings
To configure the Interlaken IP core in the parameter editor, click Installed Plug-Ins >
Interfaces > Interlaken > Interlaken PHY v10.1. The Interlaken IP core is only
available when you select the Stratix V device family.
This section describes the Interlaken PHY parameters, which you can set using the
parameter editor. Table 5–3 describes the parameters that you can set on the General
tab.
Table 5–1. Device Family Support
Device Family Support
Stratix V devices–hard PCS + hard PMA Preliminary
Other device families No support.
Table 5–2. Interlaken Performance and Resource Utilization—Stratix V Device
Number of Lanes Combinational ALUTs Logic Registers Memory Bits
1 434 263 0
4 509 346 0
10 633 517 0
15 753 659 0
20 951 916 0
Table 5–3. Parameters
Parameter Value Description
General
Device family Stratix V Specifies the device family.