User guide

Chapter 5: Interlaken PHY IP Core 5–3
Interface
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Interface
Figure 5–2 illustrates the top-level signals of the Interlaken PHY IP core.
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used to
define interfaces in the _hw.tcl.
Datapath mode Duplex, RX, TX Specifies the mode of operation as Duplex, RX, or TX mode.
Lane rate
3125 Mbps
5000 Mbps
6250 Mbps
6375 Mbps
10312.5 Mbps
Specifies the link bandwidth. The following table specifies the
frequency of the reference clock you must provide to achieve
these lane rates and the corresponding PCS frequency.
Rate Ref Clock
3125 156.25
5000 250.0
6250 312.5
6375 318.75
10312.5 515.625
Number of lanes
1–24 Specifies the number of lanes in a link over which data is striped.
Metaframe length in
words
1–8191
Specifies the number of words in a metaframe. The default value
is 2048.
Optional Ports
Add signals On/Off
When you turn this option on,
rx_parallel_data[71:69] are
included in the top-level module. These optional signals report the
status of word and synchronization locks and CRC32 errs. Refer
to Table 5–5 on page 5–5 for more information.
Create tx_coreclkin
port
On/Off
When selected
tx_coreclkin is available as input port which
drives the write side of TX FIFO, When deselected, an internal state
machine takes control.
tx_user_clkout (which is a master
tx_clockout ) drives the TX write side of FIFO. tx_user_clkout
is also available as an output port.
Create rx_coreclkin
port
On/Off
When selected
rx_coreclkin is available as input port which
drives the read side of RX FIFO, When deselected, an internal state
machine takes control.
rx_user_clkout (which is a master
rx_clockout ) drives the RX read side of FIFO. rx_user_clkout
is also available as an output port.
Table 5–3. Parameters
Parameter Value Description