User guide

Chapter 5: Interlaken PHY IP Core 5–5
Interface
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Avalon-ST RX Interface
Table 5–5 describes the signals in the Avalon-ST RX interface.
tx_clkout Output Output clock from the PCS.
tx_user_clkout Output
Master channel
tx_clkout is available when you do not create the optional
tx_coreclkin .
Table 5–4. Avalon-ST TX Signals
Signal Name Direction Description
Table 5–5. Avalon-ST RX Signals
Signal Name Direction Description
rx_parallel_data<n>[63:0] Source Avalon-ST data driven from the PCS to the FPGA fabric.
rx_parallel_data<n>[64] Source When asserted, indicates that rx_dataout[63:0] is valid.
rx_parallel_data<n>[65] Source
Indicates whether
rx_dataout[63:0] represents command or
data. When 0,
rx_dataout[63:0] is data. When 1,
rx_dataout[63:0] is control.
rx_parallel_data<n>[66] Source
This is a strobe specifying that the current data word is a
synchronization word. It is used for metaframe validation.
rx_parallel_data<n>[67] Source When asserted, indicates that the RX FIFO is full.
rx_parallel_data<n>[68] Source When asserted, indicates that the RX FIFO can accept new data.
rx_parallel_data<n>[69] Source
When asserted, indicates that the RX synchronization state machine
has locked to a single synchronization word. The synchronization
state machine must lock to 4, consecutive synchronization words to
exit the synchronization state. This signal is optional.
rx_parallel_data<n>[70] Source
When asserted, indicates that the RX synchronization state machine
has received 4 consecutive, valid synchronization words. This signal
is optional.
rx_parallel_data<n>[71] Source When asserted, indicates a CRC32 error. This signal is optional.
rx_ready Source
When asserted, indicates that the RX interface has exited the reset
state.
rx_clkout Output Output clock from the TX PCS.
rx_fifo_clr<n> Input
When asserted, the RX FIFO is flushed. This signal allows you to
clear the FIFO if synchronization is not achieved.
rx_dataout_bp<n> Sink
When asserted, enables data transmission. This signal functions as a
read enable. The RX interface has a ready latency of 1 cycle so that
rx_dataout <n> [63:0] and rx_ctrlout are valid the cycle after
rx_dataout_bp <n> is asserted.
rx_user_clkout Output
Master channel
rx_clkout is available when you do not create the
optional
rx_coreclkin .