User guide

5–8 Chapter 5: Interlaken PHY IP Core
Interface
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
PLL Interface
Table 5–9 describes the signals in the PLL interface.
TX and RX Serial Interface
Table 5–9 describes the signals in the chip-to-chip serial interface.
Stratix V Device Registers
0x081
[23:0] — Reserved —
[24] R
rx_word_lock
Asserted when the first alignment pattern is found. The RX
FIFO generates this synchronous signal.
[25] R
rx_sync_lock
Asserted by the frame synchronizer to indicate that 4 sync
words have been identified so that the RX metaframe is
synchronized.
From block: Frame synchronizer.
[26] R
rx_framing_err
Asserted by the frame synchronizer to indicate an RX
synchronization error.
From block: Frame synchronizer.
[27] R
rx_crc32_err
Asserted by the CRC32 checker to indicate a CRC error in
the corresponding RX lane.
From block: CRC32 checker.
[28] R
rx_scrm_err
Asserted by the frame synchronizer to indicate an RX
scrambler mismatch.
From block: Frame synchronizer.
[29] R
rx_sync_word_err
Asserted by the frame synchronizer to indicate that a sync
word is missing.
From block: Frame synchronizer.
[31:30] — Reserved —
Table 5–7. Interlaken Registers (Part 3 of 3)
Word
Addr
Bits R/W Register Name Description
Table 5–8. Serial Interface
Signal Name Direction Description
pll_ref_clk Input
Reference clock for the PHY PLLs. Refer to the Lane rate entry in
Table 5–3 on page 5–2 for required frequencies.
Table 5–9. Serial Interface
Signal Name Direction Description
tx_serial_data Output
Differential high speed serial output data. Using the PCML I/O
standard. Clock is recovered from the data.
rx_serial_data Input
Differential high speed serial input data. Using the PCML I/O
standard. Clock is recovered from the data.