User guide

Chapter 5: Interlaken PHY IP Core 5–9
Simulation Testbench
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Optional Clocks for Deskew
Table 5–10 describes the optional clocks that you can create to reduce clock skew.
Simulation Testbench
When you generate your Interlaken PHY IP core, the Quartus II software generates
the HDL files that define your parameterized IP core. In addition, the Quartus II
software generates an example Tcl script to compile and simulate your design in
ModelSim. Figure 5–3 illustrates the directory structure for the generated files.
Table 5–11 describes the key files and directories for the parameterized Interlaken
PHY IP core and the simulation environment which are in clear text.
Table 5–10. Serial Interface
Signal Name Direction Description
tx_coreclkin Input
When enabled
tx_coreclkin is available as input port which drives
the write side of TX FIFO. Altera recommends using this clock to
reduce clock skew. When disabled,
tx_cllkout drives the write side
the TX FIFO.
rx_coreclkin Input
When enabled
rx_coreclkin is available as input port which drives
the read side of RX FIFO. Altera recommends using this clock to
reduce clock skew. When disabled,
rx_cllkout drives the write side
the RX FIFO.
Figure 5–3. Directory Structure for Generated Files
<project_dir>
<project_dir>/<design_name> - includes PHY IP Verilog and
System Verilog design files for synthesis
<design_name>.v or .vhd - the parameterized Interlaken PHY IP core
<design_name>.qip - lists all files used in the Interlaken PHY IP design
<design_name>.bsf - a block symbol file for you Interlaken PHY IP core
<design_name>_sim/alt_interlaken_pcs = includes plain text
Verilog and System Verilog design files for simulation
modelsim_example_script.tcl = example file for compilation and
simulation of the Interlaken PHY IP core
<design_name>_sim/alt_interlaken_pcs/mentor = PHY IP encrypted
Verilog and System Verilog design files for simulation in ModelSim
when using a VHDL-only license
Table 5–11. Generated Files
File Name Description
<project_dir> The top-level project directory.
<design_name>.v or .vhd The top-level design file.
<design_name>.qip A list of all files necessary for Quartus II compilation.
<design_name>.bsf A Block Symbol File (.bsf) for your Interlaken PHY.
<project_dir>/<design_name>/
The directory that stores the HDL files that define the Interlaken PHY IP core.
These files are used for synthesis.