User guide

5–10 Chapter 5: Interlaken PHY IP Core
Simulation Testbench
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Both the Verilog and VHDL Interlaken PHY IP have been tested extensively with the
following simulators:
■ ModelSim SE
■ Synopsys VCS MX
■ Cadence NCSim
If you select VHDL for Interlaken PHY, only the wrapper generated by the Quartus II
software is in VHDL. All the underlying files are written Verilog or System Verilog. To
enable simulation using a VHDL-only ModelSim license, the underlying Verilog and
System Verilog files for the Interlaken PHY are encrypted so that they can be used
with the top-level VHDL wrapper without purchasing a mixed-language simulator.
f For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim Support chapter in volume 3 of the Quartus II Handbook.
alt_interlaken_pcs_top.v The top-level static Verilog HDL file for the Interlaken PHY IP core. It includes
parameterized port widths.
altera_wait_generate.v Generates
waitrequest for alt_interlaken_pcs.
alt_interlaken_pcs_sv.v The transceiver core and memory-mapped logic for specified number of lanes for
PMA and PLLs.
amm_slave.v The Avalon-MM slave logic.
alt_reset_ctrl_tgx_cdrauto.sv The reset controller logic.
<project_dir>/<design_name>_sim/
alt_interlaken_pcs/
The simulation directory.
modelsim_example_script.tcl
The example Tcl script to compile and simulate the parameterized Interlaken PHY
IP core. You must edit this script to include the following information:
■ The simulation language
■ The top-level Interlaken variation name
■ The name of your testbench
These variables are illustrated in Example 5–1
Table 5–11. Generated Files
File Name Description