User guide

6–2 Chapter 6: PCI Express PHY (PIPE) IP Core
Resource Utilization
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Resource Utilization
Table 6–2 shows the typical expected device resource utilization for different
configurations using the current version of the Quartus
®
II software targeting a
Stratix V GX device.
Parameter Settings
To configure the PCI Express PHY (PIPE) IP core in the parameter editor, click
Installed Plug-Ins > Interfaces > PCI Express > PCI Express PHY (PIPE) v10.1. The
PCI Express PHY PIPE IP core is only available when you select the Stratix V device
family.
This section describes the PCI Express PHY PIPE parameters, which you can set using
the parameter editor. Table 6–3 lists the settings available on General Options tab.
Table 6–2. PCI Express PHY (PIPE) Performance and Resource Utilization—Stratix V Devices
Number of Lanes
Combinational
ALUTs
Logic Registers Memory Bits PLLs
Gen1 ×1 460 285 0 2
Gen1 ×4 530 373 0 5
Gen1 ×8 590 425 0 9
Gen2 ×1 460 295 0 2
Gen2 ×4 530 373 0 5
Gen2 ×8 590 425 0 9
Table 6–3. General Options
Name Value Description
Number of lanes 1, 4, 8 The total number of PCI Express lanes
Protocol version
Gen1 (2.5 Gbps)
Gen2 (5.0 Gbps)
Specifies the protocol version. Gen1 implements
PCI Express Base
Specification 1.1.
Gen2 implements PCI Express Base
Specification 2.0.
Deserialization factor 8, 16
Specifies the width of the interface between the PHYMAC and PHY
(PIPE). Using the 16-bit interface, reduces the required clock
frequency by half at the expense of extra FPGA resources.
PIPE low latency
synchronous mode
On/Off When enabled, the rate match FIFO in low latency mode.
PLL reference clock
frequency
100 MHz
125 MHz
The PIPE standard requires a 100 MHz input clock. The 125 MHz
option is provided as a convenience which, depending on your
design, may reduce the number of clock sources you must generate
on your PCB.
Run length 40–160 Specifies the legal number of consecutive 0s or 1s.
Enable electrical idle
inferencing
True/False
When True, enables the PIPE interface to infer electrical idle instead
of detecting electrical idle using analog circuitry. For more
information about inferring electrical idle, refer to “Section 4.2.3.4
Inferring Electrical Idle” in the
PCI Express Base Specification 2.0.