User guide

Chapter 6: PCI Express PHY (PIPE) IP Core 6–3
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Interfaces
Figure 6–2 illustrates the top-level pinout of the PCI Express PHY (PIPE) IP core.
1 The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the _hw.tcl.
f For more information about _hw.tcl files, refer to Component Interface Tcl Reference
chapter in the SOPC Builder User Guide.
The following sections describe the signals in each interface.
Figure 6–2. PCI Express PHY (PIPE) Top-Level Signals (Note 1)
Note to Figure6–2:
(1) < n > is the number of lanes. The PHY (PIPE) supports ×1, ×4, ×8 operation. <d> is the total deserialization factor from the input pin to the PHYMAC
interface. <s> is the symbols size.
pipe_txdata[<n><d>-1:0]
pipetx_datak[<n><d>/8-1:0]
pipe_rxdata[<n><d>-1:0]
pipe_rxdatak[<n><d>/8-1:0]
pipe_rxvalid[<n>-1:0]
phy_phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
fixedclk
pipe_pclk
pipe_txdetectrx_loopback[<n>-1:0]
pipe_txelecidle[<n>-1:0]
pipe_txdeemph[<n>-1:0]
pipe_txcompliance[<n>-1:0]
pipe_txmargin[3<n>-1:0]
pipe_rate[1:0]
pipe_powerdown[2<n>-1:0]
pipe_rxpolarity[<n>-1:0]
pipe_rxelecidle[<n>-1:0]
pipe_phystatus[<n>-1:0]
pipe_rxstatus[3<n>-1:0]
rx_eidleinfersel
pipe_txswing[<n>-1:0]
PCI Express PIPE PHY Top-Level Signals
tx_serial_data[<n>-1:0]
rx_serial_data[<n>-1:0]
tx_ready
rx_ready
pll_locked
rx_is_lockedtodata[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_syncstatus[<d>/<n><s>-1:0]
Avalon-ST Tx
from PCI Express
PHYMAC
High Speed
Serial I/O
Avalon-MM PHY
Management
Interface
Avalon-ST Rx
to PCI Express
PHYMAC
Pipe Interface
Avalon-ST Sink
and Source
Status