User guide

6–4 Chapter 6: PCI Express PHY (PIPE) IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Avalon-ST TX Input Data from PCI Express PHYMAC
Table 6–4 describes the signals in the Avalon-ST input interface. These signals are
driven from the PCI Express PHYMAC to the PCS. This is an Avalon sink interface.
f For more information about the Avalon-ST protocol, including timing diagrams, refer
to the Avalon Interface Specifications.
Avalon-ST RX Output Data to PCI Express PHYMAC
Table 6–5 describes the signals in the Avalon-ST output interface. These signals are
driven from the PHY (PIPE) to the PHYMAC. This is an Avalon source interface.
Avalon Memory-Mapped (Avalon-MM) PHY Management Interface
The Avalon-MM PHY management block includes master and slave interfaces. This
component acts as a bridge. It transfers commands received on its Avalon-MM slave
interface to its Avalon-MM port. This interface provides access to features of the PCS
and PMA that are not part of the standard PIPE interface.
Table 6–4. Avalon-ST TX Inputs
Signal Name Dir Description
pipe_txdata[<n><d>-1:0] Sink
This is TX parallel data driven from the PCI Express PHYMAC. The ready
latency on this interface is 0, so that the PHY must be able to accept data
as soon as the PHY comes out of reset.
pipe_txdatak[<n><d>/8-1:0] Sink
Data and control indicator for the received data. When 0, indicates that
pipe_txdata is data, when 1, indicates that pipe_txdata is control.
Table 6–5. Avalon-ST RX Inputs
Signal Name Dir Description
pipe_rxdata[<n><d>-1:0] Source
This is RX parallel data driven from the PHY (PIPE). The ready latency on
this interface is 0, so that the MAC must be able to accept data as soon
as the PHY comes out of reset.
pipe_rxdatak[<n><d>/8-1:0] Source
Data and control indicator for the source data. Bit 0 correspond the low
byte of
pipe_rxdata . Bit 1 corresponds to the upper byte. When 0,
indicates that
pipe_rxdata is data, when 1, indicates that
pipe_rxdata is control.
pipe_rxvalid[<n>-1:0] Source Asserted when RX data and control are valid.