User guide

Chapter 6: PCI Express PHY (PIPE) IP Core 6–5
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Figure 6–3 illustrates the internal modules of the PCI Express PHY (PIPE) IP core.
Figure 6–3. PCI Express PIPE IP Core (Note 1)
Note to Figure6–3:
(1) Blocks in gray are soft logic. Blocks in white are hard logic.
System
Interconnect
Fabric
System
Interconnect
Fabric
Clocks
Tx Data, Datak
PIPE Control
PCI Express PIPE
Hard PCS and PMA
PCI Express PIPE and Avalon-MM Control Interface for Non-PIPE Functionality
Dynamic
Partial
Reconfiguration
PIPE Control
Tx Data, Datak
Clocks
PIPE Status
Rx Data, Datak
Valid
Clocks
Reset
Non-PIPE
Status
Non-PIPE
Control
S
Avalon-MM
Control
Non-PIPE
S
Avalon-MM
Status
Non-PIPE
S
Transceiver
Reconfiguration
Controller
Reset
Controller
PIPE reset
M
Avalon-MM
PHY
Mgmt
S