User guide
6–6 Chapter 6: PCI Express PHY (PIPE) IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
PHY Management Signals
Table 6–6 describes the signals that comprise the Avalon-MM PHY Management
interface.
Register Descriptions
Table 6–7 describes the registers that you can access over the Avalon-MM PHY
management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
Table 6–6. Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input Avalon-MM clock input.
phy_mgmt_clk_reset
Input
Global reset signal that resets the entire PHY (PIPE). A positive edge on
this signal triggers the reset controller. Refer to Figure 1–4 on page 1–7
for a timing diagram illustrating the reset sequence for a duplex channel.
phy_mgmt_address[8:0]
Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input Input data.
phy_mgmt_readdata[31:0]
Output Output data.
phy_mgmt_write
Input Write signal.
phy_mgmt_read
Input Read signal.
phy_mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave interface is unable to
respond to a read or write request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 1 of 4)
Word
Addr
Bits R/W Register Name Description
PMA Common Control and Status Registers
0x022 [31:0] R
pma_tx_pll_is_locked
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked
bit per system.
Reset Control Registers
0x041 [31:0] RW
reset_ch_bitmask
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <
n
> can be reset when
<
n
> = 1.
0x042 [1:0]
W
reset_control
(write)
Writing a 1 to bit 0 initiates a TX digital reset using the reset
controller module. The reset affects channels enabled in the
reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in the
reset_ch_bitmask.
R
reset_status
(read)
Reading bit 0 returns the status of the reset controller TX
ready bit. Reading bit 1 returns the status of the reset
controller RX ready bit.