User guide

Chapter 6: PCI Express PHY (PIPE) IP Core 6–7
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
0x044
[31:4,0] RW
reset_fine_control
You can use the reset_fine_control register to create
your own reset sequence. The reset control module,
illustrated in Figure 1–1 on page 1–2, performs a standard
reset sequence at power on and whenever the
phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are
reserved.
[1] RW
reset_tx_digital
Writing a 1 causes the internal TX digital reset signal to be
asserted, resetting all channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
[2] RW
reset_rx_analog
Writing a 1 causes the internal RX digital reset signal to be
asserted, resetting the RX analog logic of all channels
enabled in reset_ch_bitmask. You must write a 0 to
clear the reset condition.
[3] RW
reset_rx_digital
Writing a 1 causes the RX digital reset signal to be asserted,
resetting the RX digital channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
PMA Control and Status Registers
0x061 [31:0] RW
phy _ serial _ loopback
Writing a 1 to channel < n > puts channel < n > in serial
loopback mode.
0x063 [31:0] R
pma_rx_signaldetect
When channel <n> =1, indicates that receive circuit for
channel <n> senses the specified voltage exists at the RX
input buffer. This option is only operational for the PCI
Express PHY IP core.
0x064 [31:0] RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
0x066 [31:0] R
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode. Bit <n> corresponds to channel <n>.
00x067 [31:0] R
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR PLL is locked to
the reference clock. Bit <n> corresponds to channel <n>.
PCI Express PCS
0x080 [31:0] RW
Lane or group number
Specifies lane or group number for indirect addressing
which is used for all PCS control and status registers. For
variants that stripe data across multiple lanes, this is the
logical group number. For non-bonded applications, this is
the logical lane number.
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 2 of 4)
Word
Addr
Bits R/W Register Name Description