User guide

6–8 Chapter 6: PCI Express PHY (PIPE) IP Core
Interfaces
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
0x081
[31:6] R Reserved —
[5:1] R
rx_bitslipboundary
selectout
Records the number of bits slipped by the RX Word Aligner
to achieve word alignment. Used for very latency sensitive
protocols.
From block: Word aligner.
[0] R
rx_phase_comp_fifo_error
When set, indicates an RX phase compensation FIFO error.
From block: RX phase compensation FIFO.
0x082
[31:1] R Reserved —
[0] RW
tx_phase_comp_fifo_error
When set, indicates a TX phase compensation FIFO error.
From block: TX phase compensation FIFO.
0x083
[31:6] RW Reserved —
[5:1] RW
tx_bitslipboundary_selec
t
Records the number of bits slipped by the TX bit slipper in
the TX serial output. Used for very latency sensitive
protocols.
From block: TX bit-slipper.
[0] RW
tx_invpolarity
When set, the TX channel inverts the polarity of the TX data.
To block: Serializer.
0x084
[31:1] RW Reserved —
[0] RW
rx_invpolarity
When set, the RX channel inverts the polarity of the received
data. The 8B/10B decoder inverts the decoder input sample
and then decodes the inverted samples.
To block: 8B/10B decoder.
0x085
[31:4] RW Reserved —
[3] RW
rx_bitslip
When set, the word alignment logic operates in bitslip
mode. Every time this register transitions from 0 to 1, the
RX data slips a single bit.
To block: Word aligner.
[2] RW
rx_bytereversal_enable
When set enables byte reversal on the RX interface.
To block: Word aligner.
[1] RW
rx_bitreversal_enable
When set enables bit reversal on the RX interface.
To block: Word aligner.
[0] RW
rx_enapatternalign
When set, the word alignment logic operates in pattern
detect mode.
To block: Word aligner.
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 3 of 4)
Word
Addr
Bits R/W Register Name Description