User guide

Chapter 6: PCI Express PHY (PIPE) IP Core 6–9
Interfaces
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
PIPE Interface
Table 6–8 describes the signals in the PIPE interface.
0x086
[31:20] R Reserved —
[19:16] R
rx_rlv
When set, indicates a run length violation.
From block: Word aligner.
[15:12] R
rx_patterndetect
When set, indicates that RX word aligner has achieved
synchronization.
From block: Word aligner.
[11:8] R
rx_disperr
When set, indicates that the received 10-bit code or data
group has a disparity error. When set, the corresponding
errdetect bits are also set.
From block: 8B/10B decoder.
[7:4] R
rx_syncstatus
When set, indicates that the RX interface is synchronized to
the incoming data.
From block: Word aligner.
[3:0] R
rx_errdetect
When set, indicates that a received 10-bit code group has
an 8B/10B code violation or disparity error. It is used along
with Rx disparity to differentiate between a code violation
error and a disparity error, or both.
In PIPE mode, the PIPE specific output port called
pipe_rxstatus encodes the errors.
From block: 8B/10B decoder.
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 4 of 4)
Word
Addr
Bits R/W Register Name Description
Table 6–8. PIPE Interface (Part 1 of 2)
Signal Name Direction Description
pll_ref_clk Sink
This is the 100 MHz input reference clock source for the PHY PLL. You can
optionally provide a 125 MHz input reference clock by setting the PLL
reference clock frequency parameter to 125 MHz.
fixedclk Sink A 125 MHz clock used for the receiver detect circuitry.
pipe_txdetectrx_loopback Sink
This signal instructs the PHY to start a receive detection operation. After
power-up asserting this signal starts a loopback operation. Refer to section
6.4 of the
Intel PHY Interface for PCI Express (PIPE) Architecture for
a timing diagram.
pipe_txelecidle Sink
This signal forces the transmit output to electrical idle. Refer to section 7.3
of the Intel PHY Interface for PCI Express (PIPE) Architecture for
timing diagrams.
pipe_txdeemph Sink
Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it
selects the transmitter de-emphasis:
■ 1'b0: -6 dB
■ 1'b1: -3.5 dB