User guide

6–12 Chapter 6: PCI Express PHY (PIPE) IP Core
Simulation
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Simulation
When you generate your PCIe PIPE IP core, the Quartus II software generates the
HDL files that define your parameterized IP core. In addition, the Quartus II software
generates an example Tcl test script to compile and simulate your design. Figure 6–5
illustrates the directory structure for the generated files.
If you select VHDL for PCIe PIPE PHY, only the wrapper generated by the Quartus II
software is in VHDL. All the underlying files are written Verilog or System Verilog. To
enable simulation using a VHDL-only ModelSim license, the underlying Verilog and
System Verilog files for the PCIe PIPE PHY are encrypted so that they can be used
with the top-level VHDL wrapper without purchasing a mixed-language simulator.
f For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim Support chapter in volume 3 of the Quartus II Handbook.
Altera provides an example Tcl script, modelsim_example_script.tcl, with the PCI
Express PIPE PHY IP core to illustrate how to compile and simulate the core in
ModelSim. You must edit this script to include the following information:
■ The simulation language
■ The top-level PCIe PIPE PHY variation name
■ The name of your testbench
Figure 6–5. Directory Structure for Generated Files
<project_dir>
<project_dir>/<design_name> - includes PHY IP Verilog and
System Verilog design files for synthesis
pcie_phy_pipe_assignments.qip = an example of the PLL_TYPE
assignment that assigns the CMU for the TX PLL. To change the
PLL type to LC or ATX, update the PLL_TYPE option to ATX.
<design_name>.v or .vhd - the parameterized PCIe PIPE PHY IP core
<design_name>.qip - lists all files used in the PCIe PIPE PHY IP design
<design_name>.bsf - a block symbol file for you PCIe PIPE PHY IP core
<design_name>_sim/altera_pcie_phy = includes plain text
Verilog and System Verilog design files for simulation
modelsim_example_script.tcl = example file for compilation and
simulation of the PCIe PIPE PHY IP core in ModelSim
<design_name>_sim/alt_pcie_phy/mentor = PHY IP encrypted
Verilog and System Verilog design files for simulation in ModelSim
when using a VHDL-only license