User guide

Chapter 6: PCI Express PHY (PIPE) IP Core 6–13
Simulation
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Example 6–1 shows the part of the Tcl script that you must edit.
Example 6–1. Simulation Variables
#################################################################################
##
## Set your language and top level design name here
##
#################################################################################
# language = verilog (verilog variant of the PHY IP) or vhdl (vhdl variant of the PHY IP)
# defaulted to verilog
set language verilog
#################################################################################
##
## Set your top level design name here
##
#################################################################################
# dut_name = top-level Verilog variant name as generated by Qmegawiz
set dut_name <top level Verilog design name>
# tb_name = top-level testbench name.
# Can be Verilog or VHDL depending on your Modelsim license.
set tb_name <top level Verilog/VHDL testbench name>