User guide

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
7. Custom PHY IP Core
The Altera Custom PHY IP core is a generic PHY that you can customize for use in
Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom
PHY to transmit and receive data at rates of 0.600–8.5 Gbps. You can parameterize the
physical coding sublayer (PCS) to include the functions that your application
requires. The following functions are available:
■ 8B/10B encode and decode
■ Three different word alignment modes
■ Rate matching
■ Byte ordering
Your MAC layer must use the Avalon-ST to transmit and receive data from the
Custom PHY. The Avalon-ST protocol is a simple protocol designed for driving high
bandwidth, low latency, unidirectional data. To access control and status registers in
the Custom PHY, your design must include an embedded controller with an
Avalon-MM master interface. This is a standard, memory-mapped protocol that is
typically used to read and write registers and memory.
f For more information about the Avalon-ST and Avalon-MM protocols, refer to the
Avalon Interface Specifications.
Figure 7–1 illustrates the top-level signals and modules of the Custom PHY.
f For more detailed information about the Custom datapath and clocking, refer to the
“Custom Configurations with the Standard PCS” section in the Custom Transceiver
Configuration Datapath in Stratix V Devices chapter of the Stratix V Device Handbook.
Device Family Support
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■ Final support—Verified with final timing models for this device.
Figure 7–1. Custom PHY IP Core
Custom PHY IP Core
Tx Serial Data
Avalon-ST Tx and Rx
Rx Serial Data
to
ASIC,
ASSP,
FPGA,
or
Backplane
from
Custom
MAC
Stratix V FPGA
PCS:
8B/10B
Word Aligner
Rate Match FIFO
Byte Ordering
PMA:
Analog Buffers
SERDES
Avalon-MM Cntrl and Status
Avalon-ST Reconfig