User guide

7–2 Chapter 7: Custom PHY IP Core
Performance and Resource Utilization
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
■ Preliminary support—Verified with preliminary timing models for this device.
Table 7–1 shows the level of support offered by the Custom PHY IP core for Altera
device families
Performance and Resource Utilization
Accurate resource utilization numbers are not available at this time.
Parameter Settings
To configure the Custom PHY IP core in the parameter editor, click Installed Plug-Ins
> Interfaces > Transceiver PHY > Custom PHY v10.1.
General Options
The General Options tab allows you to set the basic parameters of your PHY.
Table 7–2 lists the settings available on the General Options tab.
Table 7–1. Device Family Support
Device Family Support
Arria II GX Preliminary
Arria II GZ Preliminary
HardCopy IV GX Preliminary
Stratix IV GX Preliminary
Stratix V devices–hard PCS and hard PMA Preliminary
Other device families No support
Table 7–2. General Options (Part 1 of 2)
Name Value Description
Device family
Arria II GX
Arria II GZ
HardCopy IV
Stratix IV
Stratix V
Specifies the device family.
Mode of operation
Duplex
TX
RX
You can select to transmit data, receive data, or both. Stratix IV only
supports Duplex mode in the current release.
Number of lanes 1–32 The total number of lanes in each direction.
FPGA fabric transceiver
interface width
8,10,16,20,
32,40
Specifies the total serialization factor, from an input or output pin to
the MAC-layer logic.
Enable bonding On/Off
When enabled, a single clock drives multiple lanes, reducing clock
skew.
Data rate 600–8500 Mbps Specifies the data rate.
Input clock frequency 60–700 MHz Specifies the frequency of the PLL input reference clock.
Additional Options
Enable TX Bitslip On/Off When enabled, the TX bitslip word aligner is operational.