User guide

Chapter 7: Custom PHY IP Core 7–3
Parameter Settings
December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
Figure 7–2 shows the top-level interfaces when you enable Avalon data interfaces.
Create rx_coreclkin port On/Off This is an optional clock to drive the coreclk of the RX PCS
Create tx_coreclkin port On/Off This is an optional clock to drive the coreclk of the TX PCS
Create optional port On/Off
When you turn this option on, the following signals are added to the
top level of your transceiver for each lane:
■ rx_syncstatus <n>
■ rx_is_lockedtoref <n>
■ rx_is_locedtodata <n>
■ tx_forceelecidle
■ rx_is_lockedtoref
■ rx_is_lockedtodata
■ rx_signaldetect
Avalon data interfaces On/Off
When you turn this option on, there is a separate Avalon-ST bus for
each lane which includes the control and status signals for that lane.
Layout and transmission of data is big endian. Refer to Figure 7–2.
This option must be on to use the Transceiver Toolkit.
When you turn this option off, the TX and RX interfaces are
configured as a single data and control bus, regardless of the
number of lanes. The layout and transmission of the TX and RX
buses is little endian. Refer to Figure 7–3.
Table 7–2. General Options (Part 2 of 2)
Name Value Description
Figure 7–2. Custom PHY with Avalon Interfaces Enabled